Interview with Russell Mohn from InPlay Inc.
MunEDA Analog Productivity Tools within InPlay Design Environment Russell is the Co-Founder and Vice President of RF Design at InPlay… Read More »Interview with Russell Mohn from InPlay Inc.
News
Pre-Announcement MUGM 2023
We are pleased to pre-anounce the next MunEDA User Group Meeting 2023.MUGM 2023 will take place from 16th to 17th… Read More »Pre-Announcement MUGM 2023
CASS Talks 2022 Analog (Layout) Synthesis – Prof. Helmut Graeb, Technical University of Munich, Germany – July 7, 2022 (1h 15min)
CASS Talks 2022 – Jul 8, 2022 Analog (Layout) Synthesis – Back to the Future Architectures – Prof. Helmut Graeb… Read More »CASS Talks 2022 Analog (Layout) Synthesis – Prof. Helmut Graeb, Technical University of Munich, Germany – July 7, 2022 (1h 15min)
SemiWiki – Blog – AMS, RF and Digital Full Custom IC Designs need Circuit Sizing
User Blog by Daniel Payne on 09-21-2021 at 10:00 am My career started out by designing DRAM circuits at Intel,… Read More »SemiWiki – Blog – AMS, RF and Digital Full Custom IC Designs need Circuit Sizing
SemiWiki – MunEDA CEO Interview
CEO Interview: Harald Neubauer of MunEDAby Daniel Nenni on 07-09-2021 at 6:00 am It has been my pleasure to interview… Read More »SemiWiki – MunEDA CEO Interview
A Practical Approach to Modeling ESD Protection Devices for Circuit Simulation
Lurking inside of every Mosfet is a parasitic bipolar junction transistor (BJT). Of course, in normal circuit operation the BJT… Read More »A Practical Approach to Modeling ESD Protection Devices for Circuit Simulation
Yield-optimization of CMOS full-adder design with PVT variations and NBTI
We present the detailed results of the application of mathematical optimization algorithms to transistor sizing in a full-adder cell design,… Read More »Yield-optimization of CMOS full-adder design with PVT variations and NBTI
Analog IP Migration and Verification
Introduction Semiconductor companies designing ICs for smart phones, automotive and industrial applications, CPUs, GPUs and memory components all employ teams… Read More »Analog IP Migration and Verification
Standard Cell & I/O Custom Cell Design Sizing
Introduction Standard cells are group of transistors and interconnect structures that provide boolean logic funtions (e.g. AND, OR, XOR, XNOR,… Read More »Standard Cell & I/O Custom Cell Design Sizing
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