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CASS Talks 2022 – Jul 8, 2022Analog (Layout) Synthesis – Back to the Future Architectures – Prof. Helmut Graeb

Lurking inside of every Mosfet is a parasitic bipolar junction transistor (BJT). Of course, in normal circuit operation the BJT does not play a role in the device operation. Accordingly, SPICE models for Mosfets do not behave well when the BJT is triggered. However, these… Read More »A Practical Approach to Modeling ESD Protection Devices for Circuit Simulation

We present the detailed results of the application of mathematical optimization algorithms to transistor sizing in a full-adder cell design, to obtain the maximum expected fabrication yield. The approach takes into account all the fabrication process parameter variations specified in an industrial PDK, in addition… Read More »Yield-optimization of CMOS full-adder design with PVT variations and NBTI

Introduction Semiconductor companies designing ICs for smart phones, automotive and industrial applications, CPUs, GPUs and memory components all employ teams of custom IC designers to create the highest performance chips that are as small as possible, and at the lowest costs. Efficient IP re-use is… Read More »Analog IP Migration and Verification

Introduction Standard cells are group of transistors and interconnect structures that provide boolean logic funtions (e.g. AND, OR, XOR, XNOR, inverters) or a storage function (flipflop or latch). The simplest cells are direct representations of the elemental NAND, NOR, and XOR boolean function, although cells… Read More »Standard Cell & I/O Custom Cell Design Sizing