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MUGM 2017


We are pleased to invite you to the MunEDA Users Group Meeting 2017.

MUGM 2017 will take place on November 7th & 8th (Tue/Wed), 2017 in Munich, Germany. The goal of the event is an intensive exchange of knowledge by new and experienced industrial users. MUGM provides an open forum for engineers interested in MunEDA solutions for Custom IC Design Migration, Analysis, Modelling and Optimization.

November 7 – 09:30 a.m. to 06:00 p.m.
November 8 – 09:30 a.m. to 05:30 p.m.

Le Méridien
Bayerstraße 41
80335 Munich, Germany


Tuesday, 7th November, 2017

09:30 – 10:30Registration & Welcome Coffee
10:30 – 12:00Session 1: Opening & What’s new
MunEDA – Welcome & Whats new
A. Ripp, VP Sales & Marketing, MunEDA
STMicroelectronics – MUGM 2017 Chair Opening Remarks – Pierluigi Daglio
P. Daglio, STMicroelectronics – MUGM 2017 Conference Chair
MunEDA – What’s new in WiCkeD 7.1 – Integration & R&D Roadmap
F. Schenkel, VP Research & Development, MunEDA
Empyrean / ICScape – Verification for Silicon Success
J. Xing, Empyrean
KC Chen, ICScape
MUGM Group Picture
All Participants
12:00 – 13:30Lunch Break
13:30 – 15:30Session 2: Circuit Migration & Design Retargeting
MunEDA Tutorial – (New Tool) Circuit Migration with New GUI-Version SPT 2.0
D. Plant, MunEDA
SMIC – Usage of WiCkeD in SMIC’s Flash Aplications
STMicroelectronics – Design optimization and Retargeting Strategies of Standard Cells with WiCkeD in 28nm FDSOI Technology
N. Ben Salem, STMicroelectronics
X-FAB – Technology Offering & WiCkeD in X-FAB’s AMS Reference Kit
M. Wilhelm, X-FAB
15:30 – 16:15Coffee Break – Demos & Exhibition
16:15 – 18:00Session 3: (Ultra-)High-Sigma & Yield Analysis and Optimization
MunEDA Tutorial – Worst Case Analysis Methodology with WiCkeD
M. Pronath, MunEDA
Infineon – High Sigma Verification of SRAM cells
P. Huber, Infineon
S. Schumann, Infineon
W. Kamp, Infineon
P. Micus, Infineon
MunEDA Tutorial – Monte Carlo Yield Validation – Speed-up using Sequential Testing – New BigMC Tool
V. Glöckel, MunEDA
From 19:30“MunEDA Novemberfest” – Social Event at Donisl

Wednesday, 8th November, 2017

09:30 – 10:30Session 4: Reliability in Circuit & System Level Design
MunEDA Tutorial – (New Tool) Yield Plot – Contour Line Plots of Parametric Yield and PCM performances
M. Sylvester, MunEDA
Infineon – RESIST RESilient Integrated SysTems (EU CATRENE Project RESIST)
K. Puscharsky, Infineon
G. Georgakos, Infineon
TUM – Munich Technical University –  Power-Down Synthesis for Analog Circuits
M. Neuner, Munich Technical University
10:30 – 11:00Coffee Break – Demos & Exhibition
11:00 – 12:30Session 5: Low Power & Performance Optimization for Custom IC
MunEDA Tutorial – Low-Power Circuit Sizing for Custom IC
D. Plant, MunEDA
Robert Bosch – A Generic Topology Selection Method of Analog Circuits with Embedded Circuit Sizing Demonstrated on OTA Example
A. Gerlach, Robert Bosch
STMicroelectronics – Read Path Optimization for 40nm Technology
P. Coppa, STMicroelectronics
Novatek – Robustness Optimization of AMS & Standard Cell circuits in advanced technologies
CP Huang, Novatek
12:30 – 14:00Lunch Break
14:00 – 15:30Session 6: Statistical & Optical Modelling & Yield Analysis
MunEDA Tutorial – SRAM Hierarchical Read Failure Analysis
M. Pronath, MunEDA
SKHynix – Fail analysis of Digital Temperature Sensors with WiCkeD in Non-Volatile Memory
C. Seungwan, SKHynix
S. Choi, SKHynix
LinkGlobal21 – Optic Simulation Solutions in High End Devices
J. Park, LinkGlobal21
D. Kang, LinkGlobal21
TUM – Munich Technical University – Robustness Optimization for MEMS-IC Systems
F. Burcea, Munich Technical University
15:30 – 16:00Coffee Break – Demos & Exhibition
16:00 – 17:30Session 7: Robust and High-Perfomance Design
MunEDA Tutorial – Flip-Flop High-Sigma Robustness Verification and Sizing with WiCkeD
C. Roma, MunEDA
Jena University – Optimization of a Low-power Fully Differential OTA with WiCkeD and an Introduction to Modelling the Performance Space of Front-ends for Thermoelectric Sensor Arrays
D. Schreiber, Jena University
Chipus Microelectronics S.A. – Robustness verification for trimmed references
M. Pesatti, Chipus Microelectronics
CTI – Circuit Analysis and Optimization of Voltage Reference
J.E.V. Solano, CTI
17:30 – 17:45Wrap-up & Farewell
Social Event



Weinstraße 1
80333 München

fon: +49 89 / 24 29 390
directions: Google Maps


Here you will find the password protected MUGM 2017 proceedings:

To view the password protected MUGM Proceedings, send us a request

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