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MUGM 2011


We are pleased to invite you to the MunEDA Users Group Meeting 2011.

MUGM 2011 will take place on November 24th & 25th (Thu/Fri), 2011 in Munich, Germany. The goal of the event is an intensive exchange of knowledge by new and experienced industrial users. MUGM provides an open forum for engineers interested in MunEDA solutions for Custom IC Design Migration, Analysis, Modelling and Optimization.

This years focus of the MunEDA User Group Meeting 2011 will be the special topic:

Schematic Porting between Different Processes, Assessment & Sizing Flow

November 24 – 11:00 a.m. to 06:00 p.m.
November 25 – 09:00 a.m. to 06:00 p.m.

Westin Grand Munich
Arabellastr. 6
81925 Munich, Germany

Selection of Presentation Topics at MUGM 2011:

  • SPT Schematic Porting
  • Handling Design Contraints & Sizing Rules
  • IP Porting & Technology Migration
  • Design Performance & Specification Analysis
  • Response Surface Modelling & Model Generation
  • Circuit Design Optimization & Verification
  • Statistical Circuit Analysis & Optimization
  • Multi-Testbench Environment & Corner-Based Optimization
  • Worst-Case Distance Analysis & Optimization
  • Design Shrink & Nano-scale Circuit optimization
  • Industrial Design Cases

Thursday, 24th November, 2011

10:00 – 11:00Registration & Welcome Coffee
11:00 – 12:30Session 1
11:00 – 11:15MunEDA – Welcome & Whats new
A. Ripp, VP Sales & Marketing, MunEDA
11:15 – 11:30IPGEN: Introduction – IC Design Acceleration using 1Stone®
H. Bothe, IPGEN
11:30 – 12:00STMicroelectronics: Reducing Mismatch Impact by means of Proper Biasing in Fully Differential CMOS Structures
A. Capasso, A. Colaci, STMicroelectronics
12:00 – 12:30KEYNOTE: Silicon Saxony – Network Thinking – Growing Together
A. Brüning, Chairman Silicon Saxony Workgroup IC Design, ZMDI AG
12:30 – 14:00Lunch Break
14:00 – 15:30Session 2
14:00 – 14:30What’s new in MunEDA WiCkeD 6.4 (Tool Demonstration)
M. Pronath, VP Products & Solutions, MunEDA
14:30 – 15:00STMicroelectronics: AMS Design Flow and Standardization of Analog Design Intents
P. Daglio, E. Raciti, STMicroelectronics
15:00 – 15:30Tohoku University: Analog Design Optimization with gm/Id Lookup Table Method and WiCkeD
S. Masui, Tohoku University
15:30 – 16:15Coffee & Discussion Break
16:15 – 18:00Session 3
16:15 – 16:45Toshiba: PLL Loop optimization by WiCkeD
M. Kaneko, Toshiba Semiconductor Corporation
16:45 – 17:15SyEnA: Synthesis based design of analog integrated circuits
A. Graupner, ZMDI AG
17:15 – 17:45TSMC: TSMC AMS Reference Flow & MunEDA WiCkeD
S. Chen, TSMC
17:45 – 18:00Hynix: Analysis Method for The Parasitic RC Variation Problem by WiCkeD
S. Lee, Hynix Semiconductor
18:00- 18:05Wrap-up Day 1 and Directions
A. Ripp, VP Sales & Marketing, MunEDA
From 19:30Social Event at Altes Hackerhaus

Friday, 25th November, 2011

09:00 – 10:40Session 4
09:00 – 09:25MunEDA Tools and R&D Roadmap
F. Schenkel, VP Research & Development, MunEDA GmbH
09:25 – 09:50STARC: STARCAD AMS Flow – Next Challenges
K. Tsuboi, STARC
09:50 – 10:15ON Semiconductor: Methodologies for Mismatch Sizing and Corner Verification for Automotive Applications with WiCkeD (SMAC)
J. Daniels, ON Semiconductor
10:15 – 10:40TU-Dresden/Globalfoundries: IP Porting and Resizing for High-Speed NoC
D. Walter, S. Höppner, R. Schüffny, Technical University Dresden
10:40 – 11:15Coffee & Discussion Break
11:15 – 12:30Session 5
11:15 – 11:40MunEDA: SPT Special Session – Schematic Porting (Tool Presentation)
M. Pronath, VP Products & Solutions, MunEDA GmbH
11:40 – 12:00MunEDA: SPT Special Session – Schematic Porting (Tool Demonstration)
C. Roma, MunEDA GmbH
12:00 – 12:15MunEDA: Trends and Adoption WiCkeD usemodels for Special Tasks
G. Strube, MunEDA GmbH
12:15 – 12:30IMMS: Schematic Porting with Symbol Adaption and Initial Sizing as Pre-Process for WiCkeD Optimizations
V. Boos, J. Nowak, IMMS GmbH
12:30 – 14:00Lunch Break
14:00 – 15:40Session 6
14:00 – 14:25Hynix: Design Optimization for Sensing Circuit of Resistive Memory
B. Oh, Hynix Semiconductor
14:25 – 14:50Altera: Circuit Optimization with WiCkeD design tools
JJ Lew, Altera Corporation
14:50 – 15:15TU-Dresden: Design Flow Integration of the Linearized Operating Point (LOP) Method for Fast Voltage Range Estimation with WiCkeD (SyEnA)
S. Höppner, S. Henker, J. Görner, R. Schüffny, Technical University Dresden
15:15 – 15:40STMicroelectronics : Optimization of a 2.133GHz level shifter in 28nm
N. Seller, STMicroelectronics
15:40 – 16:10Coffee & Discussion Break
16:10 – 17:45Session 7
16:10- 16:35Infineon: Parameter Calibration and Cascaded Simulations
R. Neubert, P. Rotter, Infineon Technologies
16:35 – 17:00University Rome/STMicroelectronics: Surrogate models for the analog circuit simulation based on a machine learning approach (Manon)
A. Ciccazzo, C. Vicari, STMicroelectronics
V. Latorre, S. Ludici, Sapienza University of Rome
17:00 – 17:30Survey & Hot Topic Session
M. Pronath, VP Products & Solutions, MunEDA GmbH, Germany
17:30 – 17:45Wrap-up & Farewell
Social Event

Altes Hackerhaus


Sendlingerstr. 14
80331 Munich

fon: +49 89 / 26 05 026
directions: Google Maps


Here you will find the password protected MUGM 2011 proceedings:

To view the password protected MUGM Proceedings, send us a request

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