Overview
We are pleased to invite you to the MunEDA Users Group Meeting 2012.
MUGM 2012 will take place on October 18th & 19th (Thu/Fri), 2012 in Munich, Germany. The goal of the event is an intensive exchange of knowledge by new and experienced industrial users. MUGM provides an open forum for engineers interested in MunEDA solutions for Custom IC Design Migration, Analysis, Modelling and Optimization.
This years focus of the MunEDA User Group Meeting 2012 will be the special topic:
High-sigma analysis and design optimization in deep-submicron technologies (65nm, 40nm, 28nm, 20nm and below)
Date:
October 18 – 10:30 a.m. to 06:00 p.m.
October 19 – 09:00 a.m. to 06:00 p.m.
Location:
Novotel Munich City
Hochstrasse 11
81669 Munich, Germany
Selection of Presentation Topics at MUGM 2012:
- SPT Schematic Porting
- Handling Design Contraints & Sizing Rules
- IP Porting & Technology Migration
- Design Performance & Specification Analysis
- Response Surface Modelling & Model Generation
- Circuit Design Optimization & Verification
- Statistical Circuit Analysis & Optimization
- Multi-Testbench Environment & Corner-Based Optimization
- Worst-Case Distance Analysis & Optimization
- Design Shrink & Nano-scale Circuit optimization
- Industrial Design Cases
Program
Thursday, 18th October, 2012
| 09:30 – 10:30 | Registration & Welcome Coffee |
| 10:30 – 12:45 | Session 1: Keynotes & What’s new |
| 10:30 – 10:45 | MunEDA – Welcome & Whats new A. Ripp, VP Sales & Marketing, MunEDA |
| 10:45 – 11:30 | What´s new in WiCkeD 6.5 – Integrations & R&D Roadmap F. Schenkel, VP Research & Development, MunEDA |
| 11:30 – 12:00 | Agilent GoldenGate RFIC Simulation and Analysis Software and Interoperability with MunEDA WiCkeD I. Nickeleit, C. Pujol, Agilent EESof EDA |
| 12:00 – 12:30 | GLOBALFOUNDRIES – The Company, Technologies and Design Enablement R. Meyer, GLOBALFOUNDRIES |
| 12:30 – 12:45 | Low Power MPSoC Circuit Design in GLOBALFOUNDRIES 28nm CMOS with WiCkeD S. Höppner, Technical University Dresden |
| 12:45 – 14:00 | MUGM Group Picture & Lunch Break |
| 14:00 – 15:45 | Session 2: Process Corners in WiCkeD |
| 14:00 – 14:30 | New WiCkeD Features: Corner Handling in WiCkeD 6.5 M. Pronath, VP Products & Solutions, MunEDA |
| 14:30 – 14:55 | Corner parameter generation with WiCkeD E. Gondro, K.-W. Pieper, Infineon |
| 14:55 – 15:20 | WiCkeD + CustomSim-XA for Fast Monte Carlo & WiCkeD + Cadence for Design Intent Capturing E. Raciti, STMicroelectronics |
| 15:20 – 15:45 | Sizing of FPGA cells with combination of WiCkeD and Least Squares Fitting J. Lin, Altera |
| 15:45 – 16:15 | Coffee Break – Demos & Exhibition |
| 16:15 – 18:00 | Session 3: SPT & IP Porting |
| 16:15 – 16:45 | SPT Schematic Porting Tool – Update and Application Examples M. Yakupov, MunEDA |
| 16:45 – 17:15 | Introduction Evatronix IP Cores and Services & Low/Fast Speed Differential OpAmp in 40nm TSMC with WiCkeD C. Elgert, D. Pienkowski, J. Kopanski, Evatronix |
| 17:15 – 17:45 | Circuit Porting and Re-Sizing in STARCAD-AMS Flow Y. Sasaki, STARC |
| 17:45 – 18:00 | Introduction New MunEDA E-Learning Platform B. Kahl-Grasenack, MunEDA |
| 18:00- 18:05 | Wrap-up Day 1 and Directions A. Ripp, VP Sales & Marketing, MunEDA |
| From 19:30 | Social Event at Welser Kuche |
Friday, 19th October, 2012
| 09:00 – 10:20 | Session 4: FP7 & CATRENE Funding Projects |
| 09:00 – 09:30 | FP7-Funding Projects THERMINATOR, SMAC, MANON Overview G. Gangemi, STMicroelectronics |
| 09:30 – 09:55 | WiCkeD results in the optimization of power aware current-mode devices and other prospective applications at Sapienza University of Rome Z. Abbas, M. Olivieri, University of Rome |
| 09:55 – 10:20 | Using Wicked in a Contract Research Environment E. Herzer, Fraunhofer |
| 10:20 – 11:00 | Coffee Break – Demos & Exhibition |
| 11:00 – 12:30 | Session 5: Memory Design Techniques |
| 11:00 – 11:30 | MunEDA Tutorial – SRAM & Memory Design- high-sigma yield analysis and optimization with WiCkeD C. Roma, MunEDA |
| 11:30 – 12:00 | Using Wicked for SRAM sense amp optimization M. Derevlean, L.-F. Mariut, Microsemi |
| 12:00 – 12:30 | FPGA Routing Driver Optimization G. H. Oh, Altera |
| 12:30 – 14:00 | Lunch Break |
| 14:00 – 15:30 | Session 6: Standard Cell & High-Speed I/O |
| 14:00 – 14:30 | Automated Numerical Resizing of Standard Cells in WiCkeD P. Tavares, MunEDA |
| 14:30 – 15:00 | Sizing of standard cells in worst-case process conditions in 110nm BCD9s F. Adduci, A. Capasso, A. Colaci, A. Roggero, STMicroelectronics |
| 15:00 – 15:30 | Design Centering of IO in 28nm FDSOI technology H. Degoirat, STMicroelectronics |
| 15:30 – 16:00 | Coffee Break – Demos & Exhibition |
| 16:00 – 17:30 | Session 7: Special Topics |
| 16:00 – 16:30 | Verification and Optimization of Digital Radio Receiver Sub Circuits A. Bänisch, T. Ußmüller, B. Brütting, University Erlangen |
| 16:30 – 17:00 | Educational Program for Brazilian IC Design Industry A. Schmidt, NSCAD |
| 17:00 – 17:30 | Automated, Analog Synthesis-driven Process Technology Exploration with WiCkeD M. Meissner, L. Hedrich, University Frankfurt am Main |
| 17:30 – 17:45 | Wrap-up & Farewell |
Social Event
Welser Kuche
Proceedings
Here you will find the password protected MUGM 2012 proceedings:
https://www.muneda.com/mugm/mugm-2012/proceedings/