MUGM 2010

We are pleased to invite you to the MunEDA Users Group Meeting 2010.

MUGM 2010 will take place on October 21^th & 22^th (Thu/Fri), 2010 in Munich, Germany. The goal of the event is an intensive exchange of knowledge by new and experienced industrial users. MUGM provides an open forum for engineers interested in MunEDA solutions for Custom IC Design Migration, Analysis, Modelling and Optimization.

This years focus of the MunEDA User Group Meeting 2010 will be the special topic:

Methodologies for Efficient Design-Reuse & Design Technology Transfer& Design Technology Transfer

Selection of Presentation Topics at MUGM 2010:

Thursday, 21st October, 2010

09:00 – 10:00	Registration & Welcome Coffee
10:00 – 12:00	Session 1
10:00 – 10:15	MunEDA – Welcome & Whats new A. Ripp, VP Sales & Marketing, MunEDA
10:15 – 11:00	Keynote – Infineon: IP & Re-Use – the next wave of a successful model C. Heer, Infineon Technologies AG
11:00 – 11:30	Synopsys – MunEDA: Synopsys Custom and Analog Mixed-Signal Overview & MunEDA WiCkeDTM Integration U. Trautner, Synopsys M. Pronath, MunEDA GmbH
11:30 – 12:00	STMicroelectronics – Advanced WiCkeDTM usage: A methodology for process variations impact analysis on huge circuits taking advantages of Synopsys CustomSim XA P. Daglio, E. Raciti, STMicroelectronics
12:00 – 13:20	Lunch Break
13:20 – 14:35	Session 2
13:20 – 13:45	X-FAB: Process Capabilities and Design Ecosystem of X-FAB Semiconductor Foundries O. Zinke, X-FAB Semiconductors Foundries AG
13:45 – 14:10	ZMDI & Dresden Technical University: Exploration of Feasible Voltage Ranges in Analog CMOS Circuits Using Linearized-Operating-Point Transistor Models S. Höppner, S. Henker, R. Schüffny, Technical University Dresden A. Graupner, ZMDI AG
14:10 – 14:35	MunEDA: Info about Survey, Expert’s Tools & Demo Session M. Pronath, MunEDA GmbH
14:35 – 15:10	Coffee & Discussion Break
15:10 – 16:25	Session 3
15:10 – 15:35	Anvo-Systems Dresden: WiCkeDTM for nvSRAM Multi Corner Optimization A. Scade, Anvo-Systems Dresden GmbH
15:35 – 16:00	Infineon: A new method for calculating standard deviations and correlation coefficients in modeling K.-W. Pieper, Infineon Technologies AG M. Pronath, B. Obermeier, MunEDA GmbH
16:00 – 16:25	Berkeley Design Automation: Introduction into BDA Analog FastSPICE Platform and Integration with WiCkeDTM K. Johnson, Berkeley Design Automation
16:25 – 17:00	Coffee & Discussion Break
17:00 – 18:15	Session 4
17:00 – 17:25	LSI TEC: Performance & Yield Optimization of a Switched DC/DC Converter in X-FAB XH035 Technology C. Valerio, LSI TEC G. Strube, MunEDA GmbH
17:25 – 17:50	STMicroelectronics: Embedded Flash memory Vx Linear Regulator porting from 90nm to 55nm technology while improving regulation accuracy to solve yield weakness V. Alberghina, F. Disegni , A. Ciccazzo, STMicroelectronics
17:50 – 18:15	Hynix: Voltage Generator Fail Analysis & Issue Clear with f-DFM K.-S. Kim, Hynix Semiconductor
18:15 – 18:20	Wrap-up Day 1 and Directions A. Ripp, VP Sales & Marketing, MunEDA
From 19:30	Social Event at Hofer. The “Stadtwirt”

Friday, 22th October, 2010

09:00 – 10:20	Session 5
09:00 – 09:30	MunEDA Tools and R&D Roadmap F. Schenkel, VP Research & Development, MunEDA GmbH
09:30 – 09:55	Fraunhofer/IP-Gen: Integration of Design Optimization into Automatic IP Generation with 1Stone® and WiCkeDTM K.-H. Rooch, R. Jancke, Fraunhofer IIS EAS R. Wittmann, H. Bothe, IP-Gen Rechte GmbH Matthias Sylvester, MunEDA GmbH
09:55 – 10:20	STMicroelectronics: Multi-Testbench Analysis and Optimization of an LNA for AM radio receiver in 65 nm CMOS technology with WiCkeDTM 6.3 A. Capasso, A. Colaci, F. Adduci, STMicroelectronics
10:20 – 11:05	Coffee & Discussion Break
11:05 – 12:20	Session 6
11:05 – 11:30	Infineon: Design Technology Interface & Sign-Off B. Ankele, Infineon Technologies AG
11:30 – 11:55	University of Ulm: Analysis and Improvement of a low-noise, neuronal recording-channel in austriamicrosystems AMSC35 technology with WiCkeDTM U. Bihr, J. Becker, M. Ortmanns, University of Ulm
11:55 – 12:20	Atmel: Design for Yield of High Sensitive Divider Circuits in SMARTIS technology W. Schneider, S. Kern, M. Lampp, Atmel Automotive GmbH
12:20 – 13:40	Lunch Break
13:40 – 14:55	Session 7
13:40 – 14:05	STARC: WiCkeDTM in STARCAD-AMS Design Flow T. Shirakawa, STARC Semiconductor Technology Academic Research Center
14:05 – 14:30	Altera: Applications of WiCkeD in FPGA Cell Design R. Saito, Altera
14:30 – 14:55	ON Semiconductor: Methodologies for Matching Analysis for Industrial Applications with WiCkeDTM C. Bonaldi, B. Gentinne, ON Semiconductor
14:55 – 15:50	Coffee & Discussion Break
15:50 – 17:30	Session 8
15:50 – 16:15	HYNIX: Strategy for reducing the optimization time with the best performance S. Lee, Hynix Semiconductor
16:15 – 16:40	Goethe-University Frankfurt/M.: Design Centering for Automated Topology Synthesis of Analog Circuits O. Mitea, L. Hedrich, Institute for Computer Science, Goethe-University Frankfurt/M.
16:40 – 17:05	STMicroelectronics: Extraction Methods of VHDL/VerilogA Models for Analog Blocks, Usable Inside Time Domain Simulations A. Martino, M. Micciche, A. Conte, STMicroelectronics
17:05 – 17:30	MUGM Europe 2010 User Feedback Session B. Lemaitre, M. Pronath, MunEDA GmbH
17:30 – 17:45	Wrap-up & Farewell

Hofer. The “Stadtwirt”

Here you will find the password protected MUGM 2010 proceedings:

https://www.muneda.com/mugm/mugm-2010/proceedings/