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High sigma parametric yield estimation for SRAM and standard cells


  • Verification of SRAMand standard cells poses a specific challenge to the designer because the parametric yield estimation is to be estimated for very low failure rates below 1ppb (10 –9), equivalent to >6 sigma robustness.
  • The simulation effort for standard crude Monte Carlo simulation is not feasible for such low failure rates.
  • This paper compares various approaches to solve the problem with respect to their efficiency and robustness.
  • The particular failure metrics of SRAM are considered in detail, while the applied methods for high sigma analysis are valid for standard cells as well.


Some circuits have to be verified for a very low failure rate, particularly if they are instantiated many times on one die and fail independently due to particle defects or local parametric variation (mismatch). The SRAM bitcell is the classical application case for this high-sigma analysis problem. Crude Monte Carlo simulation is often infeasible for this kind of analysis, because some circuit performances follow a non-Gaussian long tail distribution which requires a very large sample size. Special high sigma analysis methods have been developed in the past 25 years. In this paper we will compare first-order reliability model (FORM/WCD), importance sampling methods (IS), and statistical blockade (also marketed under the name high-sigma Monte Carlo (HSMC)).