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MUGM 2014


We are pleased to invite you to the MunEDA Users Group Meeting 2014.

MUGM 2014 will take place on November 17th & 18th (Mon/Tue), 2014 in Munich, Germany. The goal of the event is an intensive exchange of knowledge by new and experienced industrial users. MUGM provides an open forum for engineers interested in MunEDA solutions for Custom IC Design Migration, Analysis, Modelling and Optimization.

This years focus of the MunEDA User Group Meeting 2014 will be the special topic:

Full Custom Design Migration, Verification & Optimization in Advanced Node Technologies

November 17 – 10:30 a.m. to 06:00 p.m.
November 18 – 09:00 a.m. to 06:00 p.m.

Le Méridien
Bayerstraße 41
80335 Munich, Germany

Selection of Presentation Topics at MUGM 2014:

  • Fast and reliable full custom design migration
  • Design analysis and sizing in FinFet & FDSOI Technologies
  • Optimizing memory designs and full custom digital designs
  • Post-silicon debugging of AMS/RF circuits
  • Characterizing and optimizing standard cell libraries for statistical parametric robustness
  • Circuit sizing and constraint management for low power AMS/RF designs
  • Fast parametric verification for PVT corners and mismatch
  • Monte Carlo and Yield Analysis
  • Worst-Case Analysis and High-Sigma Statistical Analysis
  • Advances in Circuit Model Generation

Monday, 17th November, 2014

09:30 – 10:30Registration & Welcome Coffee
10:30 – 12:00Session 1: Opening & What’s new
10:30 – 10:40STMicroelectronics – MUGM 2014 Chair Opening Remarks
P. Daglio, STMicroelectronics – MUGM 2014 Conference Chair
10:40 – 10:50MunEDA – Welcome & Whats new
A. Ripp, VP Sales & Marketing, MunEDA
10:50 – 11:10MunEDA – What’s new in WiCkeD 6.7 – Integration & R&D Roadmap
F. Schenkel, VP Research & Development, MunEDA
11:10 – 11:30MunEDA – WiCkeD 6.7 Tool Demo – Enhancements & New Features
M. Yakupov, MunEDA
11:30 – 12:00ICScape – Accelerate Design Closure (MUGM 2014 EDA & Exhibition Partner)
J. Xing, M. Qin, Y.Han, ICScape
12:00 – 13:30MUGM Group Picture & Lunch Break
13:30 – 15:30Session 2: Robustness Verification and Sign-off for RF Design and Data Converters
13:30 – 14:00MunEDA – Statistical Verification and Analysis Tools
M. Pronath, VP Products & Solutions, MunEDA
14:00 – 14:25SMIC – Process related yield debug and optimization of analog IP with MunEDA WiCKeD
C. Zhu, SMIC
14:25 – 14:50Lantiq – Sign-off flow for RF design with WiCkeD in a 65nm Technology
D. Diaz-Lopez, G. Guruvaiah, B. Lemaitre, P. Pessl, Lantiq
14:50 – 15:15Novatek – S&H Sample & Hold (ADC) Mismatch Analysis and Sizing using WiCkeD
J. Chu, Novatek
15:15 – 15:30IPGEN – New layout generation techniques for variation sensitive analog circuits (MUGM 2014 EDA & Exhibition Partner)
R. Wittmann, H. Bothe, IPGEN
15:15 – 16:15Coffee Break – Demos & Exhibition
16:15 – 18:00Session 3: Aging and Reliability
16:15 – 16:40MunEDA – Reliability & Robustness Based Design Using WiCkeD (Presentation & Tool-Demo)
C. Roma, MunEDA
16:40 – 17:05STMicroelectronics – I/O Design Optimization Flow for Reliability In Advanced CMOS Nodes
V. Huard, F. Cacho, STMicroelectronics (Crolles)
17:05 – 17:25Infineon – Reliability Aware Design of Relaxation Oscillator in Advanced CMOS Technology Nodes with WiCkeD
W. Wang, G. Georgakos, G. Rott, W. Gustin, Infineon
17:25- 18:00STMicroelectronics – IOs circuit optimization activities to enhance productivity, circuit robustness and improve existing reliability flow
A. Aggarwal, STMicroelectronics (Noida)
18:00- 18:05Wrap-up Day 1 and Directions
A. Ripp, VP Sales & Marketing, MunEDA
From 19:30Social Event at Augustiner Klosterwirt

Tuesday, 18th November, 2014

09:00 – 10:15Session 4: Cell libraries and custom digital blocks
09:00 – 09:25Sapienza University Rome – Digital standard cell noise margin optimization, also considering aging effects with MunEDA WiCkeD and Synopsys MOSRA tools (MANON)
M. Olivieri, Z. Abbas, Sapienza University Rome
09:25 – 09:50Infineon – Safeguarding Holdtime Margin for Internal Scan Chain in Multibit-Register Standardcells
A. Lang, A.Huber, Infineon
09:50- 10:15Altera – Distributed Memory Design (MLAB) – design optimization and worst case analysis on memory cells, datapaths and write pulse generators with WiCkeD
G.H. Oh, G.M. Chan, Altera
10:15 – 11:15Coffee Break – Demos & Exhibition
11:15 – 13:00Session 5: Full Custom Design Migration
11:15 – 11:45MunEDA – Advances in Circuit Migration (Tutorial)
M. Pronath, VP Products & Solutions, MunEDA
11:45 – 12:10HLMC – 55nm to 40nm Bandgap porting with SPT & High gain Amp optimization with MunEDA WiCkeD
L. Ye, Y. Shan, HLMC
12:10 – 12:35Fraunhofer – Silicon Proof of the Intelligent Analog IP Design Flow using WiCkeD
B. Prautsch, Fraunhofer IIS
12:35 – 13:00MunEDA – Full-Custom Low Power Design Methodology with MunEDA WiCkeD
M. Yakupov, MunEDA
13:00 – 14:30Lunch Break
14:30 – 16:00Session 6: Robust Analog Design I
14:30 – 15:00MunEDA – Ultra High Sigma (6+ Sigma) Analysis – High Sigma is not enough (Tutorial)
V. Gloeckel, MunEDA
15:00 – 15:20STMicroelectronics – Corner Verification and Design Optimization in Smart Power & Non-Volatile Memory Technologies
E. Raciti, P. Daglio, STMicroelectronics (Agrate)
15:20 – 15:40University Frankfurt – FEATS – explorative automated topology synthesis with WiCkeD
M. Meissner, L. Hedrich, Goethe University Frankfurt/Main
15:40 – 16:00Fraunhofer – Advanced measures for OpAmp optimization with WiCkeD
E. Herzer, M. Oberst, Fraunhofer IIS
16:00 – 16:30Coffee Break – Demos & Exhibition
16:30 – 17:50Session 7: Robust Analog Design II
16:30 – 16:50STMicroelectronics – Design validation and development of RF macrocells (WebEx)
A. Capasso, A. Colaci, STMicroelectronics (Castelletto)
16:50 – 17:10ARP Microsystems – High-Voltage Automotive Analog IP Development for SOC using WiCkeD tools
A. Silaev, A. Bratsun, Y. Silaeva, ARP Microsystems
17:10 – 17:30Altera – Full-custom and Semi-custom Clock Trees Optimization using MunEDA WiCkeD – Clock Skew Matching, Clock Insertion Delay and Duty-Cycle
B. Y. Ng, Altera
17:30 – 17:50STMicroelectronics – SMAC – Smart components and Smart Systems integration (FP7-ICT-2011-7)
A. Ciccazzo, STMicroelectronics (Catania)
17:50 – 18:00Wrap-up & Farewell
Social Event

Augustiner Klosterwirt


Augustiner Str. 1
80331 Munich

fon: +49 89 / 23 23 84 80
directions: Google Maps


Here you will find the password protected MUGM 2014 proceedings:

To view the password protected MUGM Proceedings, send us a request

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