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Post-Layout Circuit Sizing Optimization in Partnership with MunEDA

Analog Design, Analog EDA


Advanced semiconductor nanometer technology nodes, together with smart IC design applications enable today very complex and powerful systems for communication, automotive, data transmission, AI, IoT, medical, industry, energy harvesting, and many more. However, more aggressive time-to-market and higher performance requirements force IC designers to look for advanced and seamless design flows, tools & methodologies to overcome these challenges. In this context for high-precision circuit applications, circuit optimization is becoming a very important step before tape-out because the increased performance variation induced by interconnect parasitics and layout-dependent effects cannot be reduced only in the pre-layout design stage.

MunEDA provides the necessary features for post-layout circuit optimization within its EDA design tool suite WiCkeD. Design engineers load circuit schematics together with DSPF post-layout netlists into MunEDA WiCkeD, parameterize the circuit interactively, and use MunEDA’s circuit optimization tools to improve the circuit performance by incremental changes of geometries, simulating the DPSF post-layout netlists. The final results are back-annotated into the schematic database to update the layout. In this webinar we’ll discuss post-layout optimization, and will show how to set up and run a test case in MunEDA’s WiCkeD circuit sizing & verification tool suite.