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Yield-optimization of CMOS full-adder design with PVT variations and NBTI

We present the detailed results of the application of mathematical optimization algorithms to transistor sizing in a full-adder cell design, to obtain the maximum expected fabrication yield. The approach takes into account all the fabrication process parameter variations specified in an industrial PDK, in addition to operating condition range and NBTI aging. The final design solutions present transistor sizing, which depart from intuitive transistor sizing criteria and show dramatic yield improvements, which have been verified by Monte Carlo SPICE analysis.

The application of a mathematical optimization methodology to the circuit design of a full-adder cell for automotive application specifications proved to be an effective way of improving the expected yield for 12 different cases of specification bounds. The obtained circuit sizing cannot be figured out by conventional manual optimization of digital cell design. Future work will focus on the application of the methodology to even more extensive performance figure se tlike noise margins and robustness to cross-talk phenomena.


Optimal NBTI Degradation and PVT Variation Resistant Device Sizing ina Full Adder Cell. In: 4th International Conference on Reliability,Infocom Technologies and Optimization (ICRITO)
J Comput Electron 3 – Abbas, Z., Khalid, U., Olivieri, M., Ripp, A., Pronath, M.

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