Lurking inside of every Mosfet is a parasitic bipolar junction transistor (BJT). Of course, in normal circuit operation the BJT does not play a role in the device operation. Accordingly, SPICE models for Mosfets do not behave well when the BJT is triggered. However, these models work just fine for most purposes. The one important application where modeling the BJT is important is for electrostatic discharge (ESD) protection circuits. ESD can be a serious threat to product yield and reliability. It is important to model ESD events before chips are fabricated to avoid problems during manufacturing and in the field. ESD events involve higher voltages and currents, that can lead to impact ionization as potential builds up across depleted junctions.
Impact ionization can cause avalanche breakdown effects, where large numbers of electrons are broken loose in an accelerating cycle. The movement of carriers during avalanche breakdown creates a current in the substrate that will trigger the BJT. Under these conditions the device is carrying additional current, creating a positive feedback loop that lowers the voltage across the device while increasing current. This is known as snapback, which wreaks havoc on traditional MOS device models.
After snapback the I-V curve shows an increase in current as voltage is increased, up to the point where there is a second avalanche that leads to thermal breakdown of the device. To properly model a Mosfet when used for an ESD application, the above behaviors must be handled by the model. Empirical data for ESD device performance can be obtained through transmission line pulse (TLP) measurements. The resulting table model is called a TLP model. This can be a useful source of information in creating an accurate SPICE model for an ESD device.
In work done at Brazil based RFID chip maker CEITEC, a macromodel was used to comprehensively model these types of devices. They worked together with MunEDA, who develops analog circuit optimization tools, to simulate and adjust the parameters in the device macromodel so that simulated results matched the measured TLP data. The work is summarized in a presentation titled “Parametric Analysis and Optimization of MOSFET Macromodels for ESD Circuit Simulation” by Robert Dettenborn. The resulting macromodel itself is made up of only standard SPICE elements.