SemiWiki – Blog – AMS, RF and Digital Full Custom IC Designs need Circuit Sizing

User Blog by Daniel Payne on 09-21-2021 at 10:00 am

My career started out by designing DRAM circuits at Intel, and we manually sized every transistor in the entire design to get the optimum performance, power and area. Yes, it was time consuming, required lots of SPICE iterations and was a bit error prone. Thank goodness that times have changed, and circuit designers can work smarter by using EDA tools that size transistors to meet goals, without all of that manual sizing and SPICE iterations.

I’ve been following EDA vendors with transistor sizing tools for many years now, and MunEDA has this technology. They are hosting a webinar on September 28th, 9AM – 10AM PDT, with the title, Optimal Circuit Sizing Strategies for Performance, Low power, and High Yield of Analog and Full-custom IP.

I asked some questions about their circuit sizing technology to learn more, prior to the webinar.

Q: Does the circuit sizing work for any IC technology: Planar CMOS, FinFET, GAA, Bipolar, BiCMOS, SiC ?

Yes, the optimization algorithms we are using for circuit sizing are developed and adapted to all today typical semiconductor process technologies like the ones mentioned by you. This is enabled by smart combinations of continuous and discrete sizing methods that have been continuously improved with process generations over the years and are meanwhile highly applicable and efficient.

Q: How large of an IP block can I optimize sizes for, in terms of MOS transistors and Resistors?

There is not really a limit by the number of single devices in your circuit. Nevertheless circuit sizing is more practical when you have circuits or blocks with a reasonable simulation time that lasts from a few seconds to a few minutes for a single simulation. Typical IP blocks used for sizing and optimizing are between a few dozen up to several hundred devices large. You have to consider that a nominal optimization run requires typically a few hundred simulations, a full yield optimization including worst-case and degradation effects can require a few thousand simulations. Depending if you expect a result within 1-2 hours or can run the optimization over the weekend or for a whole week, will have great influence on which circuits or even whole chips can be useful for such optimization runs.

Q: Do I use my own SPICE circuit simulator along with your optimization tool?

MunEDA’s tools are simulator-agnostic which means they are integrated and run with the standard industrial SPICE simulators from the large simulator vendors. But we also have integrated and run our tools with customers’ in-house simulators for many years. We are not urging the customer to use a specific simulator to run our tools. Customers like to work in their individual, quality-proven and certified design framework and simulation environment, in which other tools like MunEDA’s should be integrated smoothly and seamlessly. This is given and guaranteed for MunEDA tools for enhanced circuit migration, verification and optimization.

Read more on SemiWiki.

Summary

Learn how to automate the circuit sizing portion of your transistor-level IC designs to get the best performance in a reasonable amount of time at this webinar on September 28th, from 9:00AM to 10:AM PDT. Register online here.

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