Analog Design, Analog EDA
IC designers are tasked with meeting specifications like robustness in SRAM bit cells where the probability of a violation are lower than 1 part-per-billion (1 ppb). Another example of robustness is a Flip-Flop register that must have a probability of specification violation lower than 1 part-per-million (1 ppm). Using Monte Carlo simulation at the SPICE level for normal distributed performance with a small sample size to achieve 1 ppm requires 4.75 sigma analysis, while reaching 1 ppb increases to 6.0 sigma analysis. The problem is that for non-normal distributed performance the standard Monte Carlo approach requires a sample size that is simply too large to simulate, so a more efficient approach is required and that’s where high-sigma analysis and worst-case points come into use.
MunEDA provides the necessary features for post-layout circuit optimization within its EDA design tool suite WiCkeD. Design engineers load circuit schematics together with DSPF post-layout netlists into MunEDA WiCkeD, parameterize the circuit interactively, and use MunEDA’s circuit optimization tools to improve the circuit performance by incremental changes of geometries, simulating the DPSF post-layout netlists. The final results are back-annotated into the schematic database to update the layout. In this webinar we’ll discuss post-layout optimization, and will show how to set up and run a test case in MunEDA’s WiCkeD circuit sizing & verification tool suite.