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Analog IP Migration, Optimization and Verification

Analog Design, Analog EDA


Semiconductor companies designing ICs for smart phones, automotive and industrial applications, CPUs, GPUs and memory components all employ teams of custom IC designers to create the highest performance chips that are as small as possible, and at the lowest costs. Efficient IP re-use is a key capability of a design flow that meets time-to-market requirements and is cost-effective. When porting full custom IP to a new target process technology for the purpose of IP reuse, designers must consider many influence factors and effects, operating conditions, random variations in the manufacturing process, device aging, as well as layout-dependent effects. Sizing circuits to meet specs at all process corners and operating conditions while simultaneously minimizing power consumption and/or area is a major challenge in full custom design. Automated sizing of analog/RF and digital full custom circuits has matured greatly in recent years, evolving from early attempts at analog synthesis to modern process technology-oriented optimization tools for design centering.

In this webinar we will show:

  • automated migration of full-custom circuits
  • automated sizing methodologies that improve design quality and design time,
  • efficient statistical verification of full custom circuits after migration and sizing