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MunEDA User Group Meeting

May 16th & 17th (Tue/Wed), 2023
in Munich, Germany

  • Efficient Analog Circuit migration with MunEDA SPT Schematic Porting tool in bulk CMOS, FinFET and FD-SOI technologies
  • Linking MunEDA WiCkeD Optimizers with Intelligent IP Layout Generators for Fast Analog IC Design and IP Reuse
  • Efficient and accurate SRAM hierarchical read path verification with iterative high-sigma analysis
  • Area optimization of analog circuits
  • Corner Verification and Performance Optimization of Ultra Low Power circuits in advanced node technologies
  • Low-Voltage Analyses of Standard Cells in 22FDX Technology

September 24th (Tue), 2019
in Munich, Germany

  • Topology Migration of Sigma-Delta ADCs
  • Analog IP Migration between process technologies
  • Intelligent IP Fast Analog IC Design and Migration Using Generators
  • Corner Verification and Design Optimization in Smart Power Technologies
  • Effective analog circuit design using optimization tools
  • Power Optimization for LO Buffers and PA+matching in a low-power SoC

November 7th & 8th (Tue/Wed), 2017
in Munich, Germany

  • Read Path Optimization for 40nm Technology
  • Optimization and Evaluation of Interface Circuits
  • SRAM Hierarchical Read Failure Analysis
  • Fail analysis of Digital Temperature Sensors in Non-Volatile Memory
  • Optic Simulation Solutions in High End Devices
  • Robustness Optimization for MEMS-IC Systems

October 27th & 28th (Tue/Wed), 2015
in Munich, Germany

  • Optimization for extreme low power dissipation of bandgap designs with WiCkeD
  • Hierarchical SRAM worst case analysis
  • Fail analysis for bandgap reference in nonvolatile memory
  • Reliability aware design in FDSOI technologies
  • Optimization of Settling Time and Stability for a Low-power Fully-differential Operational Amplifier
  • Optimal NBTI Degradation and PVT Variation Resistant Device Sizing in a Full Adder Cell

November 17th & 18th (Mon/Tue), 2014
in Munich, Germany

  • Process related yield debug and optimization of analog IP
  • Sign-off Flow for RF Applications in a 65nm Technology
  • S&H Sample & Hold (ADC) Mismatch Analysis and Sizing
  • I/O Design Optimization Flow for Reliability In Advanced CMOS Nodes
  • IO circuit optimization to enhance productivity, circuit robustness and reliability
  • Design validation and development of RF macrocells
  • Safeguarding Holdtime Margin for Internal Scan Chain in Multibit-Register Standardcells
  • 55nm to 40nm Bandgap porting with SPT & High gain Amp optimization
  • Full-Semi-custom Clock Trees Optimization – Clock Skew Matching, Insertion Delay, Duty-Cycle

October 10th & 11th (Thu/Fri), 2013
in Munich, Germany

  • Power and performance optimization with transistor variables on custom circuits
  • Effects of Process Variation and Mismatch on Circuit Design: Monte Carlo and Alternatives
  • Process Characterization in 40nm and Level Shifter Optimization in 65nm (RF Design)
  • Verification and Optimization of Digital Radio Receiver Sub Circuits
  • Noise and performances analysis of a 180 nm CMOS OPAMP
  • NAND Flash Cell Sensing Sensitivity Analysis & Improvement
  • Standard Cell Performances Optimization & High Sigma Yield Analysis
  • AutoScript based design optimization flow setup for FinFET high-speed memory interfaces

October 18th & 19th (Thu/Fri), 2012
in Munich, Germany

  • Low Power MPSoC Circuit Design in GLOBALFOUNDRIES 28nm CMOS
  • Corner parameter generation
  • Sizing of FPGA cells with Least Squares Fitting
  • FPGA Routing Driver Optimization and SRAM sense amp optimization
  • Sizing of standard cells in worst-case process conditions in 110nm BCD
  • Verification and Optimization of Digital Radio Receiver Sub Circuits
  • Automated Analog Synthesis-driven Process Technology Exploration

November 24th & 25th (Thu/Fri), 2011
in Munich, Germany

  • Reducing Mismatch Impact by means of Proper Biasing in Fully Differential, Low Power CMOS Structures
  • Analog Design Optimization with gm-ID Lookup Table Method
  • PLL Loop Optimization
  • Analysis Method for Parasitic RC Variation
  • Mismatch Sizing and Corner Verification for Automotive Applications
  • IP Porting and Resizing for High-Speed NoC
  • Schematic Porting with Symbol Adaption and Initial Sizing as Pre-Process for Optimization
  • Design Optimization for Sensing Circuit of Resistive Memory
  • Optimization of a 2.133GHz level shifter in 28nm
  • Parameter Calibration and Cascaded Simulations
  • Surrogate models for the analog circuit simulation based on a machine learning approach

October 21th & 22th (Thu/Fri), 2010
in Munich, Germany

  • Exploration of Feasible Voltage Ranges in Analog CMOS Circuits Using Linearized-Operating-Point Transistor Models
  • Performance & Yield Optimization of a Switched DC/DC Converter in 350nm Technology
  • Embedded Flash memory Vx Linear Regulator porting from 90nm to 55nm technology while improving regulation accuracy to solve yield weakness
  • Voltage Generator Fail Analysis & Issue Clear with f-DFM
  • Multi-Testbench Analysis and Optimization of an LNA for AM radio receiver in 65 nm CMOS technology
  • Extraction Methods of VHDL/VerilogA Models for Analog Blocks, Usable Inside Time Domain Simulations

November 12th & 13th (Thu/Fri), 2009
in Munich, Germany

  • Worst Case Analysis and Yield Optimization of a micro-power precision OpAmp based on an advanced Offset Cancellation Chopper technique in 350nm
  • Design and characterization of a dither VCO for mixed signal application at different levels of abstraction
  • Modelling of Multi-Stage Amplifiers
  • Architectural Assessment of Design Techniques to Improve Speed and Robustness in Embedded Microprocessors
  • Ring oscillator in 65nm non volatile memory technology for low emission I/O pad buffer in 90nm CMOS low power technology for Car Radio applications
  • Design and Optimization of a High-Speed Blu-ray Disc Photodetector IC
  • Statistical Analysis and Optimization of a Sense Amplifier for very low voltage applications in CMOS 90nm Flash technology

October 09th & 10th (Thu/Fri), 2008
in Munich, Germany

  • Circuit Design Optimization Cases for Wireless Cellular Communication
  • Considering Parameter Variations in IC Design Optimization: Pareto-front Calculation
  • Response surface modelling for Industrial Application Cases
  • Digital Timing and Power Simulation with Statistical Process Variations
  • High Reliable design for High-Performance Analog Circuits

September 25th & 26th (Thu/Fri), 2007
in Munich, Germany

  • Optimization and Centering of the Basic Cells of SRAM Memories
  • Analysis and Optimization of a CMOS Mixer Circuit
  • Optimization of I/O Macro Cells
  • Robust and Reliable Analog Design for Automotive and Sensor Applications by Combining Design Centering and SOA Techniques
  • Automatic Analog Circuit Synthesis
  • Hierarchical Optimization for Phase-Locked Loops (PLL) considering Jitter, Power and Locking Time

September 19th (Tue), 2006
in Munich, Germany

  • 6T for Embedded SRAM – six sigma design
  • Reuse of Circuit Topologies
  • Design for Manufacturing (DFM) reference design flow
  • Circuit Design for Yield (DFY) for a 110dB Op-Amp for Automotive and Sensor Applications

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