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MUGM 2012 - MunEDA User Group Meeting
 Download MUGM Program-Announcement
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| Thursday, 18th October, 2012 |
| 09:30 - 10:30 |
Registration & Welcome Coffee |
| 10:30 - 12:45 |
Technical Session D1.1: Keynote & What's new |
| 10:30 |
Welcome & Whats new
A. Ripp, VP Sales & Marketing, MunEDA |
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| 10:45 |
What´s new in WiCkeD 6.5 - Integrations & R&D Roadmap
Frank Schenkel, VP Research & Development, MunEDA |
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| 11:30 |
Agilent GoldenGate RFIC Simulation and Analysis Software and Interoperability with MunEDA WiCkeD
Ingo Nickeleit/Cedric Pujol, Agilent EESof EDA |
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| 12:00 |
GLOBALFOUNDRIES - The Company, Technologies and Design Enablement
Robert Meyer, GLOBALFOUNDRIES |
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| 12:30 |
Low Power MPSoC Circuit Design in GLOBALFOUNDRIES 28nm CMOS with WiCkeD
Sebastian Höppner, Technical University Dresden |
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| 12:45 - 14:00 |
MUGM Group Picture & Lunch Break |
| 14:00 - 15:45 |
Technical Session D1.2: Process Corners in WiCkeD |
| 14:00 |
New WiCkeD Features: Corner Handling in WiCkeD 6.5
Michael Pronath, VP Products & Solutions, MunEDA |
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| 14:30 |
Corner parameter generation with WiCkeD
Elmar Gondro/Klaus-Willi Pieper, Infineon |
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| 14:55 |
WiCkeD + CustomSim-XA for Fast Monte Carlo & WiCkeD + Cadence for Design Intent Capturing
Elena Raciti, STMicroelectronics |
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| 15:20 |
Sizing of FPGA cells with combination of WiCkeD and Least Squares Fitting
James Lin, Altera |
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| 15:45 - 16:15 |
Coffee Break - Demos & Exhibition |
| 16:15 - 18:00 |
Technical Session D1.3: SPT & IP Porting |
| 16:15 |
SPT Schematic Porting Tool - Update and Application Examples
Marat Yakupov, MunEDA |
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| 16:45 |
Introduction Evatronix IP Cores and Services & Low/Fast Speed Differential OpAmp in 40nm TSMC with WiCkeD
Carsten Elgert/Dariusz Pienkowski/Jakub Kopanski, Evatronix |
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| 17:15 |
Circuit Porting and Re-Sizing in STARCAD-AMS Flow
Yoshifumi Sasaki, STARC |
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| 17:45 |
Introduction New MunEDA E-Learning Platform
Ben Kahl-Grasenack, MunEDA |
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| From 19:30 |
Social Event (See also Social Event) |
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| Friday, 19th October, 2012 |
| 09:00 - 10:20 |
Technical Session D2.1: FP7 & CATRENE Funding Projects |
| 09:00 |
FP7-Funding Projects THERMINATOR, SMAC, MANON Overview
Giuliana Gangemi, STMicroelectronics |
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| 09:30 |
WiCkeD results in the optimization of power aware current-mode devices and other prospective applications at Sapienza University of Rome
Zia Abbas/Mauro Olivieri, University of Rome |
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| 09:55 |
Using Wicked in a Contract Research Environment
Elmar Herzer, Fraunhofer |
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| 10:20 - 11:00 |
Coffee Break - Demos & Exhibition |
| 11:00 - 12:30 |
Technical Session D2.2: Memory Design Techniques |
| 11:00 |
MunEDA Tutorial - SRAM & Memory Design- high-sigma yield analysis and optimization with WiCkeD
Carlo Roma, MunEDA |
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| 11:30 |
Using Wicked for SRAM sense amp optimization
Marcel Derevlean/Loredan-Francisc Mariut, Microsemi |
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| 12:00 |
FPGA Routing Driver Optimization
Guan Hoe Oh, Altera |
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| 12:30 - 14:00 |
Lunch Break |
| 14:00 - 15:30 |
Technical Session D2.3: Standard Cell & High-Speed I/O |
| 14:00 |
Automated Numerical Resizing of Standard Cells in WiCkeD
Paulo Tavares, MunEDA |
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| 14:30 |
Sizing of standard cells in worst-case process conditions in 110nm BCD9s
Francesco Adduci/Andrea Capasso/Antonio Colaci/Andrea Roggero, STMicroelectronics |
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| 15:00 |
Design Centering of IO in 28nm FDSOI technology
Hubert Degoirat, STMicroelectronics |
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| 15:30 - 16:00 |
Coffee Break - Demos & Exhibition |
| 16:00 - 17:30 |
Technical Session D2.4: Special Topics |
| 16:00 |
Verification and Optimization of Digital Radio Receiver Sub Circuits
Andreas Bänisch/Thomas Ußmüller/Benedikt Brütting, University Erlangen |
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| 16:30 |
Educational Program for Brazilian IC Design Industry
Alonso Aymone de Almeida Schmidt, NSCAD |
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| 17:00 |
Automated, Analog Synthesis-driven Process Technology Exploration with WiCkeD
Markus Meissner/Lars Hedrich, University Frankfurt am Main |
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| 17:30 - 17:45 |
Wrap-up (MUGM & Discussion) |
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