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Download the full conference Proceedings (34 MB) |
| MUGM Europe 2010 Presentations |
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MunEDA, Welcome & Whats new
A. Ripp, MunEDA GmbH
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Infineon, IP & Re-Use - the next wave of a successful model
C. Heer, Infineon Technologies AG, Munich, Germany
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Synopsys & MunEDA, Synopsys Custom and Analog Mixed-Signal Overview & MunEDA WiCkeD Integration
U. Trautner, Synopsys, Dornach, Germany
M. Pronath, MunEDA GmbH, Munich, Germany
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STMicroelectronics, Advanced WiCkeD usage - a methodology for process variations impact analysis on huge circuits taking advantages of Synopsys CustomSim XA
P. Daglio, E. Raciti, STMicroelectronics Srl., Agrate, Italy
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X-FAB, Process Capabilities & Design Ecosystem
O. Zinke, X-FAB Semiconductors Foundries AG, Erfurt, Germany
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ZMDI & Dresden Technical University, Exploration of Feasible Voltage Ranges in Analog CMOS Circuits Using Linearized-Operating-Point Transistor Models
S. Höppner, S. Henker, R. Schüffny, Technical University Dresden, Germany
A. Graupner, ZMDI AG, Dresden, Germany
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MunEDA, Info about Survey, Expert's Tools & Demo Session
M. Pronath, MunEDA GmbH, Munich, Germany
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Anvo-Systems Dresden, WiCkeD for nvSRAM Multi Corner Optimization
A. Scade, Anvo-Systems Dresden GmbH, Dresden, Germany
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Infineon, A new method for calculating standard deviations and correlation coefficients in modeling
K.-W. Pieper, Infineon Technologies AG, Munich, Germany
M. Pronath, B. Obermeier, MunEDA GmbH, Munich, Germany
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LSI-TEC, Performance & Yield Optimization of a Switched DC-DC Converter in X-FAB XH035 Technology
C. Valerio, LSI-Tech, Sao Paulo, Brazil
G. Strube, MunEDA GmbH, Munich, Germany
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STMicroelectronics, Embedded Flash memory Vx Linear Regulator porting from 90nm to 55nm technology while improving regulation accuracy to solve yield weakness
V. Alberghina, F. Disegni , A. Ciccazzo, STMicroelectronics, Catania, Italy
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Hynix, Voltage Generator Fail Analysis & Issue Clear with f-DFM
K.-S. Kim, HYNIX Semiconductor, Icheon, Korea
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MunEDA, MunEDA Tools and R&D-Roadmap
F. Schenkel, MunEDA GmbH
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Fraunhofer & IP-GEN, Integration of Design Optimization into Automatic IP Generation with 1Stone and WiCkeD
K.-H. Rooch, R. Jancke, Fraunhofer IIS EAS, Dresden, Germany
R. Wittmann, H. Bothe, IP-Gen Rechte GmbH, Stuttgart, Germany
Matthias Sylvester, MunEDA GmbH, Munich, Germany
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STMicroelectronics, Multi-Testbench Analysis and Optimization of an LNA for AM radio receiver in 65 nm CMOS technology with WiCkeD 6.3
A. Capasso, A. Colaci, F. Adduci, STMicroelectronics Srl., Cornaredo, Italy
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Infineon, Design Technology Interface & Sign-Off
B. Ankele, Infineon Technologies AG, Villach, Austria
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Atmel, Design for Yield of High Sensitive Divider Circuits in SMARTIS Technology
W. Schneider, S. Kern, M. Lampp, Atmel Automotive GmbH, Heilbronn, Germany
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STARC, WiCkeD in STARCAD-AMS Design Flow
T. Shirakawa, STARC Semiconductor Technology Academic Research Center, Tokyo, Japan
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Altera, Applications of WiCkeD in FPGA Cell Design
R. Saito, Altera, Santa-Clara, USA
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ON Semiconductor, Methodologies for Matching Analysis for Industrial Applications with WiCkeD
C. Bonaldi, B. Gentinne, ON Semiconductor, Vilvoorde-Oudenaarde, Belgium
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Hynix, Strategy for reducing the optimization time with the best performance
S. Lee, HYNIX Semiconductor, Icheon, Korea
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Goethe University Frankfurt am Main, Design Centering for Automated Topology Synthesis of Analog Circuits
O. Mitea, L. Hedrich, Institute for Computer Science, Goethe-University Frankfurt/M., Germany
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STMicroelectronics, Extraction Methods of VHDL-VerilogA Models for Analog Blocks, Usable Inside Time Domain Simulations
A. Martino, M. Micciche, A. Conte, STMicroelectronics Srl., Catania, Italy
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