MunEDA GmbH - Application Areas

IP Porting, IP Reuse & Technology Migration

Most IP Porting projects are challenging because analog-/mixed-signal designs, RF designs, IP libraries and memory cells and even entire SoCs must be migrated often in a short time, mostly by a very limited number of designers. There is no simple rule for shrinking AMS/RF, I/O and full-custom digital designs. Every block needs adjustment of geometries, biasing, etc. even if specs don't change. Therefore, it is necessary to migrate and port the schematics individually to be conforming to technology constraints, or to meet enhanced functionality or performance specifications.

IP porting can be versatile, and it includes different tasks:

Horizontal Porting: Migrating IP from one technology node to the same node of a different foundry due to second sourcing, fab consolidation or foundry migration.
Vertical Porting: Migrating IP from a technology node to a smaller one, usually from the same fab or foundry.

IP Migration Challenges

Different device parameters (vth, etc.) require adjustment of biasing and small-signal parameters
W, L shrinking is desirable, but not as simple as digital
Some devices (mimcaps, inductors, etc.) may or may not be available, or may be of a quite different type
Circuit topology may need modification
Layout shrinking in integrated technologies is insufficient

MunEDA WiCkeD contains specialized tools for using for IP Porting, IP Reuse and Re-Targeting as well as Technology Migration. These include tools for sensitivity analysis, constraint editing and management, performance optimization and statistical analysis and optimization. WiCkeD helps the designer to save time and effort in using automated tools for easier migration and re-targeting of existing IP and circuits to new process technology.

After conversion of the circuit topology from source technology to target technology by the designer MunEDA WiCkeD tools can be used to size the ported topology.

Therefore it is recommended to use the following consecutive verification & optimization steps:

Simulation & Functional Analysis with industrial standard SPICE simulator from WiCkeD simulation GUI
Feasibility Optimization with WiCkeD FEA: checks constraints and ensured saturation conditions
Nominal Optimization with WiCkeD DNO: meets performance specifications for nominal & PVT corners
Nominal Optimization with WiCkeD DNO: meets performance specifications for worst-case operation corners
Yield Optimization with WiCkeD YOP: minimizes the variance of performance parameters

In addition to MunEDA WiCkeD enhanced analysis and diagnosis tools within the given design environment.

Benefits - IP Porting with MunEDA WiCkeD

Designers can achieve large benefits when using MunEDA WiCkeD tools within their IP Porting and sizing projects:

Consistent IP Porting flow of existing design databases between different process technologies
Makes sizing process for IP porting faster and more efficient
Can be applied to individual cells or entire libraries
Improves designers' productivity and convenience
Efficient re-sizing in the new target technology

Datasheet - IP Porting with MunEDA WiCkeD

Download Datasheet IP Porting with MunEDA WiCkeD Tools

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Andreas Brüning, Director Technology Office, ZMD AG, Dresden:
"After testing MunEDA's design and yield optimization tool WiCkeD in some very successful pilot projects, we chose it for analysis and optimization of analog and mixed-signal circuits and towards increased yield and robustness of our golden IP library."

Customer Success - IP Porting, IP Reuse & Technology Migration

STMicroelectronics, Embedded Flash memory Vx Linear Regulator porting from 90nm to 55nm technology while improving regulation accuracy to solve yield weakness

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[Link] Faraday - IP porting & Analog Synthesis Automation Platform using WiCkeD^TM

[Link] ZMDI - Analog IP Porting

Posters

Faraday Technology Corporation - An IP Porting System for Analog Libraries

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ZMDI-MunEDA - Conversion and Optimization Flow for Analog IP Porting

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Technical Papers

ZMDI-MunEDA - Analog IP Porting by Topology Conversion and Optimization, IP - ESC 2009 (Best Paper Award)

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Thomas Hsieh, R&D Associate Vice President, Faraday Technology Corp.:
"MunEDA's WiCkeD showed the capability as an optimization tool in the key role of our IP porting project. The capacity is a general issue for the simulation-based optimization tool. We successfully could demonstrate the circuit optimization process through the comprehensive GUI and script based flow."