Design for Manufacturability & Design for Yield
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Configurations Overview

1: WiCkeDTM Light Configuration: Specification-driven Yield Analysis & Global Optimization
2: Analog IP Porting System
3: Design for Manufacturability flow for nominal design analysis and optimization
4: Design for Yield flow for statistical circuit analysis and optimization



WLC1

IPP2

DFM3

DFY4

DFM3-DFY4
Modules Tools
xxxxxBAS - WiCkeDTM Basic (required): Constraint Editor, Sensitivity, Parallel Simulation
  x xNOD - Nominal Diagnosis
  x xSCG - Parameter Screening
  x xWCO - Worst Case Operation
x  xxMCA - Monte Carlo Analysis
   xxWCA - Worst Case Analysis
   xxWCD - Worst Case Diagnosis
   xxMMA - Mismatch Analysis
 xx xFEA - Feasibility Optimization
 xx xDNO - Deterministic Nominal Optimization
x x xGNO - Global Nominal Optimization
   xxYOP - Yield Optimization
 x   SCR - Scripting Interface
(x)(x)(x)(x)(x)Interface to Cadence® Spectre®
(x)(x)(x)(x)(x)Interface to Synopsys® HSPICE®
(x)(x)(x)(x)(x)Interface to Mentor® Eldo®