MunEDA GmbH - Products

MunEDA – WiCkeD^TM List of all Tools

Individual Tools Configuration: Just click on the "[remove]" functions of the tools you currently not want to include into your desired configuration. As soon your configuration is finished just print out or learn more details when clicking on the "Read more..." links of each individual tool.

Tool Logo	Tool Short Description	Features	Applications

[remove]	SPT – Schematic Porting Tool MunEDA SPT Schematic Porting Tool supports designers with an automated schematic migration, replacing cells with corresponding cells in the new library. Read more...	Automated Schematic Porting – 10-100X faster than manual porting Flexible Property Mapping Handles MOS, R, C, and other properties Walks hierarchically through the schematics Automated Shrinking Configurable for many source and target processes

[remove]	BAS – WiCkeD^TM Basic WiCkeD Basic delivers a powerful basic feature compilation to enable the circuit designer to do enhanced topology analysis, constraint setup and management as well as different analysis types for circuit performance, parameter sensitivity and correlation. WiCkeDTM is fully integrated into standard design environments and using standard industrial simulators. Read more...	Constraint Management Sensitivity Analysis Design Parameter Analysis Process Parameter Analysis Operating Parameter Analysis Parameter Sweeps Performance Setup Graphical User Interface Parallel Simulation Interface	Specification Driven Design Sensitivity Analysis Performance Trade-off Analysis

[remove]	CED – Constraint Editor The WiCkeD Constraint Editor generates a complete constraint and parameter setup for the circuit analysis and optimization process. Therefore, the Constraint Editor retrieves data from the design environment e.g. directly from the schematic editor or from a netlist. Read more...	Constraint Editor Automated Parameter Setup Automatic Parameterization Automated Topology Structure Recognition Configurable Topology Structure Recognition Graphical User Interface	Circuit Topology Analysis Circuit Constraints Analysis Technology Constraints Analysis

[remove]	NOD – Nominal Diagnosis NOD enables the user to perform powerful analyses based on typical (nominal) process characteristics. The designer gets insight into dependencies between performances and parameters with very small simulation effort. Read more...	Analysis of nominal design Manual optimization of nominal design Parameter influence analysis Parameter redundancy analysis Constraint limits Performance improvements	Nominal Design Analysis Trade-off analysis of design parameters and performances

[remove]	SCG – Parameter Screening With SCG the circuit designer can filter during the design analysis and optimization process parameters with large and low influence on the performances and constraints. This can significantly reduce required simulation efforts. Read more...	Automated Screening & Masking of design, process, and operation parameters Filtering based on sensitivities Interactive Filtering Automatic Filtering Simulation performance improvements	Nominal Design Analysis Design Parameter Influence Analysis Absolute Parameter Influence Relative Parameter Influence Reduction of simulation efforts

[remove]	WCO - Worst Case Operation WCO is a powerful analysis tool that calculates and displays worst-case operating conditions. A special Worst-Case operation algorithm is minimizing/maximizing performances for lower/upper specification. Read more...	Worst Case Operating Corners Calculation of worst-case performance values Non-linear performance characteristics Circuit Reliability Analysis Circuit Robustness Analysis	Calculation of Worst-Case Operating Conditions Minimize performance for lower/upper specification Maximize performance for lower/upper specification

[remove]	FEA – Feasibility Optimization FEA enables the circuit designer to automatically optimize the operating point of its design to fulfill all electrical/geometrical constraints. A feasible design represents a first step towards successful circuit optimization. Read more...	Topology Analysis and Diagnosis Constraint fulfillment Algorithm Find Closest Algorithm Find Central Minimum change of constraints Maximum over fulfillment of constraints	Topology Functional Analysis Feasible Design Constraint Handling and Constraint Management Initial Design Point Analysis Start for Circuit Optimization

[remove]	DNO – Deteministic Nominal Optimization DNO is a powerful optimization engine for automatic nominal circuit optimization. DNO improves circuit performance values by changing design parameters with unique gradient-based optimization algorithms to perform an automatic performance optimization. DNO is able to fully consider operating conditions and structural constraints on an user-defined and optional base. Read more...	Parameter-Specification driven Least-Square Algorithm Parameter Distance Algorithm SQP Algorithm Consideration of operating conditions	Automatic Performance Optimization Automatic Constraint Fulfillment Specification Driven Optimization

[remove]	GNO – Global Nominal Optimization GNO is a state-of-the-art stochastic optimization engine especially for optimization of circuits with non-linear behaviour. This enables to find global maxima and minima of the performance function. MunEDA GNO is able to fully consider operating conditions and structural constraints on an user-defined and optional base. Read more...	Performance specification bounds Parameters to modify Genetic Sizing Algorithms Adjustable number of iterations	Design Space Exploration Find initial sizing Find global maxima and minima of the performance function in design space

[remove]	MCA - Monte Carlo Analysis MCA is one of the most powerful Monte Carlo Analysis tools on the market. Containing numerous tools and features for parametric yield analysis, contributors for yield loss can be detected and eliminated. Read more...	Parametric Yield Analysis Mismatch Analysis Influence Analysis of Process Variations Contributor Analysis Performance distributions Means, standard deviations, correlations Margin distributions Global process information Local process information (Matching) Scatter plots Data export	Variation-aware design analysis Variation Design Analysis Parametric Yield Analysis Mismatch Analysis Calculation of standard deviations

[remove]	WCA - Worst Case Analysis With WCA the circuit designer is able to estimate the worst-case conditions for individual performance specifications. It determines partial and total yields for given specifications on circuit performances. Read more...	Total yield estimation Partial yield estimation Consideration of operating conditions Consideration of process parameters Global process variations Local process variations (Mismatch) Sensitivity-Based Algorithms Evolutionary/Genetic Algorithms	Variation-aware design analysis High-Yield Design Analysis Mismatch Analysis Partial and total yields for given specifications on circuit performance Worst Case Analysis Robustness Analysis

[remove]	WCD - Worst Case Diagnosis WCD enables the designers to interactively improve and optimize the robustness for their designs. MunEDA´s unique silicon proven Worst Case Distance methodology also enables the interactive optimization for yield. Read more...	Specification driven design Parametric Yield Analysis Interactive Yield Improvement Contributor Diagnosis Worst Case Distance Algorithms Design Parameter Influence	Variation-aware design analysis Manual adjustment of a design with consideration of process variations Manual design centering Analysis of Worst-Case Analysis results

[remove]	MMA - Deterministic Mismatch Analysis MMA identifies and analyses mismatch-relevant transistor pairs on selected circuit performances. The variance of these local variations will be analyzed based on dependencies of device pair geometries. Read more...	Mismatch pair detection Analysis of matching constraints Local process variations influence Information for yield optimization Fast deterministic algorithms Performances by mismatch effects	Variation-aware design analysis Mismatch Analysis Matching Analysis Reliability Analysis

[remove]	YOP - Yield Optimization YOP is the world´s unique and most powerful tool for automatic performance and yield optimization based on global and local process parameter variations. Active optimization of 6 sigma robustness levels and more are now possible. Read more...	Automatic Yield Optimization 6+ sigma design optimization Consideration of operating conditions High efficient optimization engines Low simulation effort compared to Monte Carlo or Stochastic algorithms	Variation-aware design optimization Design Centering Yield Optimization Robustness Optimization Reliability Optimization

[remove]	RSM - Model Generation RSM generates Response Surface Models of the analyzed circuit. This enables the designer to speed up simulations and therefore the circuit analysis and optimization steps. Furthermore sub-blocks of larger systems can be modeled. Read more...	Response Surface Modelling Model Generation in larger systems Different Modeling Types: Polynomial, Radial Basis Functions, ARBI, PolyRBI, a.o. Speeding up circuit simulation effort Exports models in Verilog-A and VHDL-AMS	Simulation Speed-up Large circuit and IP performance and statistical analysis Statistical variation analysis based on circuit models

[remove]	SCR - Scripting Interface SCR is providing a powerful programmable interface to be used with the complete MunEDA tool set for integration of customer-specific algorithms and environments. The scripting feature can also be used to integrate MunEDA modules with other tools or to customize the user interface. Two languages are available for scripting: Tcl and Python. Both are popular scripting languages and are well integrated with MunEDA tools. SCR supports different editors and debuggers. Read more...	Tcl/Tk Phyton Matlab R / S-Plus	Netlist- and Script-based designflows Automated IP Porting Flow IP & Library Design

[remove]	SFI - Simulator / Framework, Interface MunEDA WiCkeD tools are fully integrated in industrial standard design frameworks and SPICE, FastSPICE and behavioral simulators of leading EDA vendors and partners. Find a selection of the main supported designframeworks and simulators below or contact us for further information. Read more... Supported EDA Design Frameworks [Link] Cadence - Virtuoso ADE Analog Design Environment (IC5, IC6-L, XL, GXL) [Link] Mentor Graphics - Design Architect IC / IC Station [Link] Synopsys - Custom Designer SE Supported Simulators / SPICE [Link] Cadence - Spectre, SpectreRF, UltraSim, MMSIM [Link] Mentor Graphics - Eldo, EldoRF, AdvanceMS, AdiT [Link] Synopsys - HSpice, HSIM, NanoSIM, XA [Link] Berkeley Design Automation - AFS Analog FastSPICE Platform Verilog-A, VHDL-AMS Industrial Inhouse Simulators Waveform Viewer Support All standard waveform viewers supported from inside WiCkeD		Parallel Simulator Interface Designframework Interface

[remove]	MTB - Multi-Testbench Environment The Multi-Testbench Environment enables the usage of multiple netlists and testbenches in WiCkeD. Read more...	Usage of multiple netlists, e.g. different testbenches or same netlists with different library corners Matching of physically identical instances, including mismatch Defining matching properties (matching of design parameters) Several analysis of the same type are possible, e.g. three different transient simulations	Multitestbench-analysis Multi-Corner-Analysis PVT-Corner Analysis PVT-Corner Optimization Worst-Case Corner Analysis Multi-State Design Analysis