|
 |
|
|
 |
Download the full conference Proceedings (31 MB) |
| MUGM Europe 2011 Presentations |
 |
Welcome & What’s new, MunEDA
A. Ripp, MunEDA GmbH
|
Download Document: 
|
 |
 |
Introduction - IC Design Acceleration using 1Stone®, IPGEN
H. Bothe, IPGEN, Germany
|
|
Download Document:
|
|
 |
Reducing Mismatch Impact by means of Proper Biasing in Fully Differential, Low Power CMOS Structures, STM
A. Capasso, A. Colaci, STMicroelectronics Srl., Italy
|
Download Document:
View presentation with Adobe Presenter
|
|
 |
Silicon Saxony - Network Thinking - Growing Together, ZMDI
A. Brüning, Chairman Silicon Saxony Workgroup IC Design, ZMDI AG, Germany
|
Download Document:
View presentation with Adobe Presenter
|
|
 |
News & Updates WiCkeD 6.4, MunEDA
M. Pronath, VP Products & Solutions, MunEDA GmbH, Germany
|
Download Document:
View presentation with Adobe Presenter
|
|
 |
AMS Design Flow & Standardization of Analog Design Intent, STM
P. Daglio, E. Raciti, STMicroelectronics Srl., Italy
|
Download Document:
View presentation with Adobe Presenter
|
|
 |
Analog Design Optimization with gm-ID Lookup Table Method and WiCkeD, Uni Tohoku
S. Masui, Tohoku University, Japan
|
|
Download Document:
|
|
 |
PLL Loop Optimization by WiCkeD, Toshiba
M. Kaneko, Toshiba Semiconductor Corporation, Japan
|
Download Document:
View presentation with Adobe Presenter
|
|
 |
SyEnA - Synthesis based design of analog integrated circuits, ZMDI
A. Graupner, ZMDI AG, Germany
|
|
Download Document:
|
|
 |
TSMC AMS Reference Flow & MunEDA WiCkeD, TSMC
S. Chen, TSMC, Taiwan
|
|
Download Document:
|
|
 |
Analysis Method for The Parasitic RC Variation Problem by WiCkeD, Hynix
S. Lee, Hynix Semiconductor, Korea
|
Download Document:
View presentation with Adobe Presenter
|
|
 |
MunEDA Tools and R&D Roadmap, MunEDA
F. Schenkel, VP Research & Development, MunEDA GmbH, Germany
|
Download Document:
View presentation with Adobe Presenter
|
|
 |
STARC - STARCAD-AMS Flow Next Challenges, STARC
K. Tsuboi, STARC, Japan
|
Download Document:
View presentation with Adobe Presenter
|
|
 |
Methodologies for Mismatch Sizing and Corner Verification for Automotive Applications with WiCkeD, On Semi
J. Daniels, ON Semiconductor, Belgium
|
Download Document:
View presentation with Adobe Presenter
|
|
 |
IP Porting and Resizing for High-Speed NoC, TU Dresden
D. Walter, S. Höppner, R. Schüffny, Technical University Dresden, Germany
|
|
Download Document:
|
|
 |
MunEDA WiCkeD - SPT Schematic Porting Tool, MunEDA
M. Pronath, VP Products & Solutions, MunEDA GmbH, Germany
|
|
Download Document:
|
|
 |
Trends and Adoption - WiCkeD use-models for Special Tasks, MunEDA
G. Strube, MunEDA GmbH, Germany
|
|
Download Document:
|
|
 |
Schematic Porting with Symbol Adaption and Initial Sizing as Pre-Process for WiCkeD Optimizations, IMMS
V. Boos, J. Nowak, IMMS GmbH, Germany
|
|
Download Document:
|
|
 |
Design Optimization for Sensing Circuit of Resistive Memory, Hynix
B. Oh, Hynix Semiconductor, Korea
|
Download Document:
View presentation with Adobe Presenter
|
|
 |
Circuit Optimization with WiCkeD design tools, Altera
JJ Lew, Altera Corporation, Malaysia
|
Download Document:
View presentation with Adobe Presenter
|
|
, TU Dresden.jpg) |
Design Flow Integration of the Linearized Operating Point (LOP), TU Dresden
S. Höppner, S. Henker, J. Görner, R. Schüffny, Technical University Dresden, Germany
|
Download Document:
View presentation with Adobe Presenter
|
|
, STM.jpg) |
Optimization of a 2.133GHz level shifter in 28nm (with WiCkeD), STM
N. Seller, STMicroelectronics, France
|
Download Document:
View presentation with Adobe Presenter
|
|
 |
Parameter Calibration and Cascaded Simulations, Infineon
R. Neubert, P. Rotter, Infineon Technologies, Germany
|
|
Download Document:
|
|
, STM.jpg) |
Surrogate models for the analog circuit simulation based on a machine learning approach (ManOn), STM
A. Ciccazzo, C. Vicari, STMicroelectronics Srl., Italy
V. Latorre, S. Ludici, Sapienza University of Rome, Italy
|
|
Download Document:
|
|
|
|
WebEx
