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cadence and MunEDA Cadence Design Systems Inc.


MunEDA in Cadence Connections

MunEDA has been a member of the Cadence Connections Partner Program since 2004. For more information please check the Cadence Connections Program Partner Pages

Cadence-MunEDA Integration Collaterals and Datasheets

DATASHEET - Cadence, MunEDA:
MunEDA WiCkeDTM Interface to Cadence® Virtuoso® Analog Design Environment and Cadence® Virtuoso® Multi-Mode Simulation with Spectre® Circuit Simulator and UltraSim® Full-Chip Simulator

Cadence Interoperability Guide - MunEDA WiCkeDTM:
Improve Design Performance and Yield


WiCkeD fully integrated into Cadence Virtuoso platform

WiCkeD ideally complements the Cadence Virtuoso Analog Design Environment and is seamlessly integrated into both .cdb and open access versions. This enables the designer to access and utilize all WiCkeD tools easily from the familiar Cadence Virtuoso based design environment.

WiCkeD Interface to Cadence Virtuoso Analog Design Environment

WiCkeD can be started directly from the Virtuoso Analog Design Environment Tools menu with fully automated annotation of the design data from and back-annotation to schematic & netlist.

WiCkeD Interface to Cadence Virtuoso Schematic Editor

WiCkeD directly annotates the design and hierarchy data from the Cadence Virtuoso Schematic Editor followed by a fully automatic parameterization of schema-tic and netlist design parameters as well as constraint setup and editing. Specifications for circuit analysis and optimization can be easily entered in the WiCkeD Constraint Editor. Parameterized devices and hierarchies can be highlighted from WiCkeD Constraint Editor directly in the schematic editor. The technology setup (nominal, corner, mismatch, global statistics) will be done automatically from the pdk using a technology based configuration file.

WiCkeD Interface to Cadence Virtuoso Multi-Mode-Simulation

WiCkeD fully supports industry standard simulator Spectre Circuit Simulator and UltraSim Full-Chip Simulator. A part of Virtuoso Multi-Mode-Simulation solution. Using third party SPICE from your Cadence Virtuoso environment is also supported by the WiCkeD simulator interface environment.


Cadence-MunEDA Publications & Customer Reference Cases
  • PDF[Link] STMicroelectronics: Analysis and Optimization of Mismatch in Analog Designs
  • PDF[Link] Infineon: Fast Automatic Sizing of a Charge-Pump Phase-Locked Loop based on behavioral Models Circuit Reference Case: Phased Locked Loop (PLL) in 90nm CMOS Technology
  • PDF[Link] austriamicrosystems: Yield Optimisation of Power-On Reset Cells and Functional Verification - Circuit Reference Case: Power-on Reset Cell (POR) in 350nm CMOS Technology
  • PDF[Link] Atmel, Bosch, Cadence, Infineon, MunEDA, Qimonda: VeronA - Verification of Analog Circuits - BMBF Project 01 M 3079 edacentrum
  • PDF[Link] Fraunhofer: Analysis and optimization of a CMOS mixer circuit with WiCkeD
  • PDF[Link] X-FAB, IMMS, MunEDA: Technology Setup for WiCkeD in X-FAB CMOS and BiCMOS Processes for Automotive and Sensor Applications
  • PDF[Link] ZMD, X-FAB, MunEDA: Verification of Safe Operating Area (SOA) Constraints in Analog Circuits (Poster)
  • PDF[Link] ZMD, X-FAB, MunEDA: Verification of Safe Operating Area (SOA) Constraints in Analog Circuits (Paper)
  • PDF[Link] IMMS, Melexis, X-FAB, Infineon, Cadence, MunEDA: Workshop Design Centering
  • PDF[Link] ZMD, MunEDA: Analog IP Porting by Topology Conversion and Optimization
  • PDF[Link] Cadence, MunEDA: MunEDA WiCkeDTM Interface to Cadence® Virtuoso® Analog Design Environment and Cadence® Virtuoso® Multi-Mode Simulation with Spectre® Circuit Simulator and UltraSim® Full-Chip Simulator - Joint Datasheet

Cadence-MunEDA Weblinks & Press Releases
  • WWW[Link] VeronA-Project with Cadence and MunEDA wins the 2010 EDA Achievement Award
  • WWW[Link] ZMD and MunEDA presented paper for Verification Methodology of Analog and Mixed Signal Circuits at CDNLive! EMEA in Munich 18-20 May 2009
  • WWW[Link] Cadence Interoperability Guide & MunEDA WiCkeDTM: Improve Design Performance and Yield