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| Agenda MunEDA Technical-Forum Anaheim 2008 |
| 09.30 - 10.00 |
Registration & Welcome Coffee |
| 10.00 - 10.15 |
Welcome & What´s new
A. Ripp, VP Sales & Marketing, MunEDA GmbH |
| 10.15 - 11.00 |
Introduction into Front-End Design for Manufacturability & Yield DFM-DFY with MunEDA´s WiCkeDTM
M. Pronath, VP Products & Solutions, MunEDA GmbH |
| 11.00 - 11.20 |
Coffee & Discussion Break |
| 11.20 - 12.00 |
TUM: Considering parameter variations in IC design optimization: Pareto-front calculation and other ideas
U. Schlichtmann, Technical University of Munich |
| 12.00 - 12.45 |
STMicroelectronics: Industrial Designflow Integration and Application Cases with WiCkeDTM DFM-DFY Tools in STMicroelectronics UNICAD Design Environment
P. Daglio, STMicroelectronics
P. Rolandi, STMicroelectronics |
| 12.45 - 13.30 |
Lunch & Talks |
| 13.30 - 14.00 |
WiCkeDTM 6.0: Software Tutorial & Release Updates
V. Glöckel, MunEDA GmbH |
| 14.00 - 14.30 |
Faraday Technologies Corp.: Analog IP Migration & Design Synthesis Platform with WiCkeDTM
KC Wu, Faraday Technology Corp.
M. Pronath, VP Products & Solutions, MunEDA GmbH |
| 14.30 - 14.45 |
Fraunhofer Institute: A new Approach for the Circuit Design with Manufacturing Variations
KC Wu, Faraday Technology Corp.
M. Dietrich, Head Modelling & Simulation, Fraunhofer IIS EAS |
| 14.45 - 15.00 |
Coffee & Discussion Break |
| 15.00 - 15.15 |
Special Topic: Integration of WiCkeDTM into Mentor Graphics Custom IC Flow with IC Studio and Eldo®
V. Glöckel, MunEDA GmbH |
| 15.15 - 15.40 |
Special Topic: Automatic Flow for Library Optimization based on Synopsys HSpice® and WiCkeDTM
T. Vogels, MunEDA Inc. |
| 15.40 - 16.00 |
Presentation of Industrial Application Cases & Discussion
M. Pronath, VP Products & Solutions, MunEDA GmbH |
| 16.00 |
Wrap-up Discussion & Farewell Coffee |
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