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U. Schlichtmann, H. Gräb, Technical University Munich, Germany
R. Sommer, E. Hennig, Infineon Technologies AG, Munich, Germany
F. Schenkel, MunEDA GmbH, Munich, Germany
T. Ifstroem, Robert Bosch GmbH, Reutlingen, Germany
Systematic Analog/Mixed-Signal Design - Yield Optimization of Analog Circuits with WiCkeD
MEDEA+ Forum 2004, November 2004, Paris, France
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U. Schlichtmann, G. Stehr, T. Massier, H. Gräb, Technical University Munich, Germany
R. Sommer, E. Hennig, Infineon Technoologies AG, Munich, Germany
F. Schenkel, A. Ripp, MunEDA GmbH, Munich, Germany
Systematischer Analog/Mixed-Signal-Entwurf und Designsicherheit
EKOMPASS04, May 2004, Hannover, Germany
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G. Stehr, M. Pronath, F. Schenkel, H. Gräb, K. Antreich, Technical University Munich, Germany
M. Pronath, F. Schenkel, Munich, Germany
http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1257655
Initial Sizing of Analog Integrated Circuits by Centering within Topology-Given Implicit Specifications
ICCAD 2003, November 2003, San Jose, CA, USA
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A. Ripp, MunEDA GmbH, Munich, Germany (Chair)
R. Sommer, E. Hennig, Infineon Technologies AG, Munich, Germany
F. Schenkel, M. Pronath, A. Ripp, MunEDA GmbH, Munich, Germany
Tutorial Design for Manufacturability: Statistical Analysis and Yield Optimization of analog integrated circuits
ANALOG03, September 2003, Heilbronn, Germany
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R. Schwencker, F. Schenkel, M. Pronath, H. Gräb, Technical University Munich, Germany
Dimensionierung analoger integrierter Schaltungen mittels adaptiver Worst-Case-Parametersätze
GMM/ITG Diskussionssitzung Entwurf von Analogschaltungen 2002, May 2002, Bremen, Germany
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R. Schwencker, F. Schenkel, M. Pronath, H. Gräb, Technical University Munich, Germany
Analog Circuit Sizing using Adaptive Worst-Case Parameter Sets
DATE02, February 2002, Paris, France
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F. Schenkel, M. Pronath, H. Gräb, Technical University Munich, Germany
WiCkeD 3: Design Centering and Mismatch Analysis for Analog Integrated Circuits
DATE02, February 2002, Paris, France
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R. Schwencker, F. Schenkel, M. Pronath, H. Gräb, Technical University Munich, Germany
Analog Circuit Synthesis Based on an Iterative Relaxed Worst-Case Formulation
DATE 2002, February 2002, Munich, Germany
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F. Schenkel, M. Pronath, S. Zizala, R. Schwencker, H. Gräb, K. Antreich, Technical University Munich, Germany
Mismatch Analysis and Direct Yield Optimization by Spec-Wise Linearization and Feasibility-Guided Search
DAC 2001, June 2001, Las Vegas, NV, USA
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F. Schenkel, M. Pronath, H. Gräb, K. Antreich, Technical University Munich, Germany
A Fast Method for Identifying Matching-Relevant Transistor Pairs
CICC 2001, May 2001, San Diego, CA,USA
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K. Antreich, J. Eckmüller, H. Gräb, M. Pronath, F. Schenkel, R. Schwencker, S. Zizala, Technical University Munich, Germany
WiCkeD: Analyse und Dimensionierung analoger Schaltungen unter Berücksichtigung von Mismatch
ITG/GI-Workshop 2000, November 2000, Darmstadt, Germany
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K. Antreich, J. Eckmüller, H. Gräb, M. Pronath, F. Schenkel, R. Schwencker, S. Zizala, Technical University Munich, Germany
WiCkeD: Analog circuit synthesis incorporating mismatch
CICC 2000, May 2000, Orlando, FL, USA
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R. Schwencker, F. Schenkel, H. Gräb, K. Antreich, Technical University Munich, Germany
The Generalized Boundary Curve - A Common Method for Automatic Nominal
DATE 2000, March 2000, Paris, France
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F. Schenkel, M. Pronath, S. Zizala, R. Schwencker, H. Gräb, K. Antreich, Technical University Munich, Germany
Direct Yield Optimization of Analog Integrated Circuits Considering Global and Local Process Tolerances
Technical Report TUM-LEA-00-1, , Munich, Germany
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F. Schenkel, M. Pronath, H. Gräb, K. Antreich, Technical University Munich, Germany
Detection of Matching Transistor Pairs Using Circuit Sensitivities
Technical Report TUM-LEA-00-2, , Munich, Germany
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