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Tutorials, Publications, Customer and Reference Cases Following, is a list of MunEDA publications, customers and reference cases regarding Design for Manufacturability and Yield projects as well as additional references and detailed References by Circuit Class. You can also download our Customer Reference Booklet.
	ZMDI - MunEDA DAC2011 June 2011, San Diego, USA Conversion and Optimization Flow for Analog IP Porting Circuit Reference Case: OTA - Operational Transconductance Amplifier Download Document:
	Melexis - IMMS - TU Dresden - TU Ilmenau - MunEDA [Link] V. Boos, J. Nowak, S. Henker, S. Hoeppner, M. Sylvester, H. Grimm Strategies for Initial Sizing and Operating Point Analysis of Analog Circuits DATE 2011 - Design Automation and Test in Europe Conference, March 2011, Grenoble, France Download Document:
	STMicroelectronics - MunEDA Antonio Colaci, Gianluigi Boarin, Andrea Roggero, Lorenzo Civardi, Carlo Roma, Gunter Strube, Andreas Ripp and Michael Pronath Systematic Analysis & Optimization of Analog/Mixed-Signal Circuits Balancing Accuracy and Design Time SBCCI 2010 - 23rd Symposium on Integrated Circuit and Systems Design, September 2010, Sao Paulo, Brazil Download Document:
	H. Gräb, Xin Pan, Technical University Munich, Germany Reliability analysis of analog circuits by lifetime yield prediction using worst-case distance degradation rate ISQED 2010, March 2010, San Jose, CA, USA Download Document: [Link]
	U. Sobe, A. Graupner, E. Böhme ZMD AG, Dresden, Germany A. Ripp, M. Pronath, MunEDA GmbH, Munich, Germany Analog IP Porting by Topology Conversion and Optimization IP - ESC 2009, December 2009, Grenoble, France Download Document:
	U. Sobe, K.-H. Rooch, D. Mörtl, A. Graupner, ZMD AG, Dresden, Germany A. Ripp, M. Pronath, MunEDA GmbH, Munich, Germany Robust Analog Design for Automotive Applications by Design Centering With Safe Operating Areas May 2009, Semiconductor Manufacturing, IEEE Transactions on Download Document: [Link]
	U. Schlichtmann, M. Schmidt, Technical University Munich, Germany M. Pronath, V. Glöckel, MunEDA GmbH, Munich, Germany H. Kinzelbach, Infineon Technologies AG, Munich, Germany M. Dietrich, U. Eichler, J. Haase, Fraunhofer IIS/EAS Dresden, Germany Digital Design at a Crossroads DATE09, April 2009, Nice, France Download Document:
	STMicroelectronics - Infineon - X-FAB - MunEDA - IMMS EUROPEAN NANOELECTRONICS Forum 2008 November 2008, Paris, France HONEY – Highly Optimized Design Methods for Yield and Reliability 2A713 Download Document:
	X-FAB - ZMD - MunEDA ZuE 2008 - Reliability and Design September 2008, Ingolstadt, Germany Verification of Safe Operating Area (SOA) Constraints in Analog Circuits Download Document:
	U. Sobe, K.-H. Rooch, D. Mörtl, A. Graupner, ZMD AG, Dresden, Germany A. Lerch, X-Fab Semiconductor Foundries AG, Erfurt, Germany M. Pronath, MunEDA GmbH, Munich, Germany Verification of Safe Operating Area (SOA) Constraints in Analog Circuits ZuE 2008 - Reliability and Design, September 2008, Ingolstadt, Germany Download Document:
	X-FAB - IMMS - MunEDA edaWorkshop 2008 May 2008, Hannover, Germany Technology Setup for WiCkeD in X-FAB CMOS and BiCMOS Processes for Automotive and Sensor Applications Download Document:
	Fraunhofer - MunEDA edaWorkshop 2008 May 2008, Hannover, Germany Analysis and Optimization of a CMOS Mixer Circuit with WiCkeD Download Document:
	Atmel, Bosch, Cadence, Infineon, MunEDA, Qimonda VeronA - Verification of Analog Circuits - BMBF Project 01 M 3079 edacentrum DATE08, March 2008, Munich, Germany Download Document:
	K.-H. Rooch, U. Sobe, ZMD AG, Dresden, Germany A. Ripp, M. Pronath, MunEDA GmbH, Munich, Germany Robust Analog Design for Automotive Aplications by Design Centering with Safe Operating Areas ISQED´08, March 2008, San Jose, CA, USA Download Document:
	STMicroelectronics - Infineon - X-FAB - MunEDA - IMMS MEDEA+ Annual Forum 2007 November 2007, Budapest, Hungary HONEY – Highly Optimized Design Methods for Yield and Reliability Download Document:
	STMicroelectronics - Mentor Graphics - MunEDA September 2007, Munich, Germany Designflow Architecture and Integration of Statistical Sizing Methods in STMicroelectronics Non-Volatile-Memory (NVM) and Automotive Flow based on MunEDA-WiCkeD and Mentor-Eldo Download Document:
	Faraday Technology Corporation June 2007, Hsin-Chu/Munich, Taiwan/Germany An IP Porting System for Analog Libraries Circuit Reference Case: Controllable delay line in 90nm CMOS Technology Download Document:
	Infineon - Fraunhofer - MunEDA - Sigma65 June 2007, Hannover, Germany 65nm Technology Based Modelling and Analysis Methodologies based on Variations Circuit Reference Case: Digital Cell Libraries (SSTA) in 65nm CMOS Technology Download Document: [Link]
	A. Ripp, MunEDA GmbH, Munich, Germany Challenges of reliability oriented design strategies for analog and mixed-signal circuits MEDEA-DAC 2007, May 2007, Grenoble, France Download Document:
	V. Boos, IMMS GmbH, Erfurt, Germany Graph Theoretical Approach for Initial Sizing of Analog Circuits DASS 2007, May 2007, Dresden, Germany Download Document:
	H. Gräb, Technical University Munich, Germany Analog Design Centering and Sizing April 2007, Munich, Germany Download Document: [Link]
	A. Ripp, MunEDA GmbH, Munich, Germany (Chair) R. Sommer, IMMS - TU Ilmenau M. Pronath, MunEDA GmbH, Munich, Germany Design Tutorial DfY-DfM - Design for Yield and Manufacturability ZuD 2007 - Reliability and Design, March 2007, Munich, Germany Download Document:
	K.-H. Rooch, U. Sobe, ZMD AG, Dresden, Germany M. Pronath, MunEDA GmbH, Munich, Germany Robust Analog Design for Automotive Applications by Design Centering ZuD 2007 - Reliability and Design, March 2007, Munich, Germany Download Document:
	ZMD - ZFoundry September 2006, Dresden, Germany ZMD-ZFoundry Circuit Design-for-Yield (DFY) using WiCkeD - 110dB Op-Amp for Automotive and Sensor Applications Circuit Reference Case: High Gain Operational Transconductance Amplifier in 600nm CMOS Technology Download Document:
	O. Eisenberger, G. Rappitsch, austriamicrosystems AG, Unterpremstaetten, Austria B. Obermeier, A. Ripp, M. Pronath, MunEDA GmbH, Munich, Germany Yield Optimisation of Power-On Reset Cells and Functional Verification - Power-on Reset Cell (POR) in 350nm CMOS Technology ANALOG06, September 2006, Dresden, Germany Download Document:
	G. Rappitsch, O. Eisenberger, austriamicrosystems AG, Unterpremstaetten, Austria B. Obermeier, A. Ripp, M. Pronath, MunEDA GmbH, Munich, Germany Experimental Verification of Simulation Based Yield Optimization for Power-On Reset Cells CICC 2006, September 2006, San Jose, CA, USA Download Document: [Link]
	K.-H. Rooch, U. Sobe, ZMD AG, Dresden, Germany M. Pronath, MunEDA GmbH, Munich, Germany Circuit Design-for-Yield (DFY) for a 110dB Op-Amp for Automotive and Sensor Applications - Circuit Reference Case: Fully differential folded cascode OTA in 600nm CMOS Technology ANALOG06, September 2006, Dresden, Germany Download Document:
	T. Fischer, T. Nirschl, D. Schmitt-Landsiedel, B. Lemaitre, Infineon Technologies, Munich, Germany Modelling of the parametric yield in decananometer SRAM-Arrays - Sense-Amplifier for SRAM-Memory in 90nm and 65nm CMOS Technology Advances in Radio Science 2006, September 2006, Katlenburg-Lindau, Germany Download Document:
	austriamicrosystems July 2006, Unterpremstaetten, Austria austriamicrosystems Design for Manufacturability (DFM) reference design flow using MunEDA DFM-DFY tool WiCkeD Circuit Reference Case: Power-on Reset (POR) in 350nm CMOS Technology Download Document:
	STMicroelectronics July 2006, Agrate, Italy Analysis and Optimization of Mismatch in Analog Designs with WiCkeD Circuit Reference Case: A) Sense Amplifier for SRAM in 130nm CMOS Technology B) Bandgap Voltage Reference in 90nm CMOS Technology Download Document:
	Qimonda - TUM DAC 2006 July 2006, San Francisco, CA, USA A CPPLL Hierarchical Optimization Methodology Considering Jitter, Power and Locking Time Circuit Reference Case: Charge Pump - Phased Locked Loop (PLL) in 90nm CMOS Technology Download Document: [Link]
	M. Pronath, MunEDA GmbH, Munich, Germany Design for Yield Concepts for Analogue and Mixed-Signal Circuits MEDEA-DAC 2006, May 2006, Prien, Germany Download Document:
	A. Ripp, MunEDA GmbH, Munich, Germany ANASTASIA+ - Successful bridge from basic methodology research to industrial design tool delivery MEDEA-DAC 2006, May 2006, Prien, Germany Download Document:
	A. Ripp, MunEDA GmbH, Munich, Germany (Chair) M. Bühler, J. Koehl, IBM Deutschland Entwicklung GmbH, Böblingen, Germany J. Bickford, J. Hibbeler, IBM Inc., Burlington, USA U. Schlichtmann, Technical University Munich, Germany R. Sommer, Infineon Technologies AG, Munich, Germany M. Pronath, A. Ripp, MunEDA GmbH, Munich, Germany DATE 2006 Special Session: DFM/DFY Design for Manufacturability and Yield - influence of process variations in digital, analog and mixed-signal circuit design DATE06, March 2006, Munich, Germany Download Document: [Link]
	A. Ripp, MunEDA GmbH, Munich, Germany Robustness and Reliability - Facing new Quality Levels for Automotive ICs with Design for Yield EuroDesignCon 2005, October 2005, Munich, Germany Download Document:
	Infineon Technologies BMAS 05 September 2005, San Jose, CA, USA Fast Automatic Sizing of a Charge-Pump Phase-Locked Loop based on behavioral Models Circuit Reference Case: Phased Locked Loop (PLL) in 90nm CMOS Technology Download Document:
	M. Pronath, A. Ripp, MunEDA GmbH, Munich, Germany Advanced Mathematical and Computational Methods fort he Design Centering of Electronic Circuits SCEE Summer School 2005, September 2005, Capo D'Orlando, Sicily, Italy Download Document:
	R. Sommer, Infineon Technologies AG, Munich, Germany M. Pronath, MunEDA GmbH, Munich, Germany Seamless Analog/Mixed-Signal Top-Down Design Flow - Applications from Circuit Sizing, Design Centering, and Symbolic Circuit Analysis MEDEA-DAC 2005, May 2005, Château des Mesnuls, France Download Document: [Link]
	STMicroelectronics ISQED 05 March 2005, San Jose, CA, USA How Circuit Analysis and Yield Optimization Can Be Used to Detect Circuit Limitations before Silicon Results Circuit Reference Case: Bandgap Voltage Reference in 90nm CMOS Technology Download Document:
	IMMS EUROSOI 05 January 2005, Granada, Spain Linear Regulators for High Temperature Applications Circuit Reference Case: Linear LDO Regulator in 1.0µm SOI-Technology Download Document:
	Bosch - Infineon MEDEA+ Forum 2004 November 2004, Paris, France Systematic Analog/Mixed-Signal Design - Yield Optimization of Analog Circuits with WiCkeD Circuit Reference Case: A) Complementary folded cascode transconductance Amplifier in 130nm CMOS B) Operational Amplifier for Automotive Applications in 800nm BiCMOS Technology Download Document:
	U. Schlichtmann, H. Gräb, Technical University Munich, Germany R. Sommer, E. Hennig, Infineon Technologies AG, Munich, Germany F. Schenkel, MunEDA GmbH, Munich, Germany T. Ifstroem, Robert Bosch GmbH, Reutlingen, Germany Systematic Analog/Mixed-Signal Design - Yield Optimization of Analog Circuits with WiCkeD MEDEA+ Forum 2004, November 2004, Paris, France Download Document:
	Infineon - MunEDA - TUM Ekompass Workshop May 2004, Hannover, Germany Systematic Analog/Mixed-Signal Design and Design Accuracy Circuit Reference Case: FC OpAmp in 130nm CMOS Technology Download Document:
	U. Schlichtmann, G. Stehr, T. Massier, H. Gräb, Technical University Munich, Germany R. Sommer, E. Hennig, Infineon Technoologies AG, Munich, Germany F. Schenkel, A. Ripp, MunEDA GmbH, Munich, Germany Systematischer Analog/Mixed-Signal-Entwurf und Designsicherheit EKOMPASS04, May 2004, Hannover, Germany Download Document:
	Infineon - MunEDA - MEDEA - ANASTASIA DATE04 February 2004, Paris, France Industrial Design Tutorial - DFY/DFM - Design for Yield and Manufacturability Circuit Reference Case: Complementary-folded Cascode OpAmp (130nm) Download Document:
	A. Ripp, MunEDA GmbH, Munich, Germany (Chair) R. Sommer, E. Hennig, Infineon Technologies AG, Munich, Germany M. Pronath, A. Ripp, MunEDA GmbH, Munich, Germany Design Tutorial DFY/DFM - Design for Yield and Manufacturability DATE04, February 2004, Paris, France Download Document:
	IMMS - Melexis - X-FAB - Infineon - Cadence - MunEDA Workshop Design Centering 2004 January 2004, Erfurt, Germany Design Efficiency and Yield Improvement in Analog Design with WiCkeD Download Document:
	G. Stehr, M. Pronath, F. Schenkel, H. Gräb, K. Antreich, Technical University Munich, Germany M. Pronath, F. Schenkel, Munich, Germany http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1257655 Initial Sizing of Analog Integrated Circuits by Centering within Topology-Given Implicit Specifications ICCAD 2003, November 2003, San Jose, CA, USA Download Document:
	austriamicrosystems ESSCIRC September 2003, Estoril, Portugal Statistical Spice Modelling for analog circuit design, G. Rappitsch, MOS-AK: Advanced Compact Modeling Workshop Circuit Reference Case: Standard Library OpAmp Download Document: [Link]
	Infineon - MunEDA ANALOG03 September 2003, Heilbronn, Germany Tutorial Design for Manufacturability: Statistical Analysis and Yield Optimization of analog integrated circuits Download Document:
	A. Ripp, MunEDA GmbH, Munich, Germany (Chair) R. Sommer, E. Hennig, Infineon Technologies AG, Munich, Germany F. Schenkel, M. Pronath, A. Ripp, MunEDA GmbH, Munich, Germany Tutorial Design for Manufacturability: Statistical Analysis and Yield Optimization of analog integrated circuits ANALOG03, September 2003, Heilbronn, Germany Download Document:
	J. Fischer, E. Amirante, D. Schmitt-Landsiedel, Technical University Munich, Germany F. Randazzo, G. Iannaccone, Universita degli Studi di Pisa, Italy Reduction of the Energy Consumption in Adiabatic Gates by Optimal Transistor Sizing September 2003, Munich, Germany Download Document: [Link]
	Infineon - MunEDA DATE03 March 2003, Munich, Germany Design for Manufacturablity Circuit Reference Case: Fully-Cascode OpAmp in 180nm CMOS Technology Download Document:
	Infineon Technologies MEDEA+ DAC 2002 October 2002, Stresa Lago Maggiore, Italy Top-Down Design Methods for Mixed-Signal Applications Download Document:
	Infineon Technologies July 2002, Munich, Germany Mixed Signal - Design for Systems on Chip with WiCkeD Download Document:
	R. Schwencker, F. Schenkel, M. Pronath, H. Gräb, Technical University Munich, Germany Dimensionierung analoger integrierter Schaltungen mittels adaptiver Worst-Case-Parametersätze GMM/ITG Diskussionssitzung Entwurf von Analogschaltungen 2002, May 2002, Bremen, Germany Download Document: [Link]
	M. Pronath, H. Gräb, K. Antreich, Technical University Munich, Germany Simulation und Testentwurf für Floating-Gate Defekte (FGD) in analogen integrierten Schaltungen GMM/ITG Diskussionssitzung Entwurf von Analogschaltungen 2002, May 2002, Bremen, Germany Download Document: [Link]
	M. Pronath, H. Gräb, K. Antreich, Technical University Munich, Germany Design of Optimal Implicit Tests for Parametric Faults considering Errors of Test Stimuli and Measurements European Test Workshop 2002, May 2002, Korfu, Greece Download Document: [Link]
	M. Pronath, H. Gräb, K. Antreich, Technical University Munich, Germany Der Einfluss von Ungenauigkeiten im Teststimulus auf den Test analoger Schaltungen ITG/GI-Workshop 2002, March 2002, Bad Herrenalb, Germany Download Document: [Link]
	R. Schwencker, F. Schenkel, M. Pronath, H. Gräb, Technical University Munich, Germany Analog Circuit Sizing using Adaptive Worst-Case Parameter Sets DATE02, February 2002, Paris, France Download Document: [Link]
	M. Pronath, H. Gräb, K. Antreich, Technical University Munich, Germany A Test Design Method for Floating Gate Defects (FGD) in Analog Integrated Circuits DATE02, February 2002, Paris, France Download Document:
	F. Schenkel, M. Pronath, H. Gräb, Technical University Munich, Germany WiCkeD 3: Design Centering and Mismatch Analysis for Analog Integrated Circuits DATE02, February 2002, Paris, France Download Document: [Link]
	R. Schwencker, F. Schenkel, M. Pronath, H. Gräb, Technical University Munich, Germany Analog Circuit Synthesis Based on an Iterative Relaxed Worst-Case Formulation DATE 2002, February 2002, Munich, Germany Download Document:
	M. Pronath, H. Gräb, K. Antreich, Technical University Munich, Germany On Parametric Test Design for Analog Integrated Circuits considering Error in Measurement and Stimulus Modeling, Simulation and Optimization of Integrated Circuits 2001, November 2001, Oberwolfach, Germany Download Document: [Link]
	S. Zizala, J. Eckmüller, Infineon Technologies, Munich K. Antreich, H. Gräb, Technical University of Munich The sizing rules method for analog integrated circuit design ICCAD 2001, November 2001, San Jose, CA, USA Download Document:
	F. Schenkel, M. Pronath, S. Zizala, R. Schwencker, H. Gräb, K. Antreich, Technical University Munich, Germany Mismatch Analysis and Direct Yield Optimization by Spec-Wise Linearization and Feasibility-Guided Search DAC 2001, June 2001, Las Vegas, NV, USA Download Document: [Link]
	M. Pronath, H. Gräb, K. Antreich, Technical University Munich, Germany Estimation of the Influence of Test Stimulus Precision on Test Quality for Parametric Faults in Analog Integrated Circuits IEEE Mixed Signal Test Workshop 2001, June 2001, Atlanta, GA, USA Download Document:
	F. Schenkel, M. Pronath, H. Gräb, K. Antreich, Technical University Munich, Germany A Fast Method for Identifying Matching-Relevant Transistor Pairs CICC 2001, May 2001, San Diego, CA,USA Download Document: [Link]
	V. Glöckel, M. Pronath, H. Gräb, Technical University Munich, Germany Deterministischer parametrischer Testentwurf für analoge integrierte Schaltungen mit Testbeobachtungen unter Anwendung von Ergebnissen aus dem Toleranzentwurf ITG/GI-Workshop 2001, February 2001, Miesbach, Germany Download Document:
	MEDEA – Innovative Design Techniques Speed Analogue/Digital IC Development December 2000, Munich, Germany Download Document:
	K. Antreich, J. Eckmüller, H. Gräb, M. Pronath, F. Schenkel, R. Schwencker, S. Zizala, Technical University Munich, Germany WiCkeD: Analyse und Dimensionierung analoger Schaltungen unter Berücksichtigung von Mismatch ITG/GI-Workshop 2000, November 2000, Darmstadt, Germany Download Document: [Link]
	M. Pronath, V. Gloeckel, H. Gräb, Technical University Munich, Germany A Parametric Test Method for Analog Components in Integrated Mixed-Signal Circuits ICCAD 2000, November 2000, San Jose, CA, USA Download Document: [Link]
	K. Antreich, J. Eckmüller, H. Gräb, M. Pronath, F. Schenkel, R. Schwencker, S. Zizala, Technical University Munich, Germany WiCkeD: Analog circuit synthesis incorporating mismatch CICC 2000, May 2000, Orlando, FL, USA Download Document: [Link]
	R. Schwencker, F. Schenkel, H. Gräb, K. Antreich, Technical University Munich, Germany The Generalized Boundary Curve - A Common Method for Automatic Nominal DATE 2000, March 2000, Paris, France Download Document: [Link]
	M. Pronath, Technical University Munich, Germany Testentwurf für analoge Komponenten gemischt analog-digitaler Schaltungen basierend auf der Auswertung des Übertragungsverhaltens AES 2000, January 2000, Karlsruhe, Germany Download Document: [Link]
	R. Schwencker, J. Eckmüller, H. Gräb, K. Antreich, Technical University Munich, Germany Automating the Sizing of Analog CMOS Circuits by Consideration of Structural Constraints DATE 1999, March 1999, Munich, Germany Download Document: [Link]
	S. Zizala, J. Eckmüller, H. Gräb, K. Antreich, Technical University Munich, Germany Effiziente Modellierung integrierter analoger CMOS-Schaltungen durch Berücksichtigung von Struktureigenschaften ANALOG99, February 1999, Munich, Germany Download Document:
	J. Eckmüller, G. Strube, H. Gräb, Technical University Munich, Germany Diagnose für integrierte Analogschaltungen ANALOG96, October 1996, Berlin, Germany Download Document:
	K. Antreich, H. Gräb, C. Wieser, Technical University Munich, Germany Circuit Analysis and Optimization Driven by Worst-Case Distances IEEE Transactions CAD, January 1994, , Download Document: [Link]
	K. Antreich, H. Gräb, Technical University Munich, Germany Circuit Optimization Driven by Worst-Case Distances ICCAD 1991, November 1991, Santa Clara, CA, USA Download Document: [Link]
	M. Pronath, H. Gräb, K. Antreich, Technical University Munich, Germany Parametric Test of Mixed-Signal ICs under Consideration of the Impact of Test Stimulus Imprecisions Technical Report TUM-LEA-01-1, , Munich, Germany Download Document: [Link]
	M. Pronath, H. Gräb, K. Antreich, Technical University Munich, Germany Fault Simulation and Test Design for Floating Gate Defects in Analog Integrated Circuits Using Power-Down Circuitry Technical Report TUM-LEA-01-3, , Munich, Germany Download Document: [Link]
	F. Schenkel, M. Pronath, S. Zizala, R. Schwencker, H. Gräb, K. Antreich, Technical University Munich, Germany Direct Yield Optimization of Analog Integrated Circuits Considering Global and Local Process Tolerances Technical Report TUM-LEA-00-1, , Munich, Germany Download Document: [Link]
	F. Schenkel, M. Pronath, H. Gräb, K. Antreich, Technical University Munich, Germany Detection of Matching Transistor Pairs Using Circuit Sensitivities Technical Report TUM-LEA-00-2, , Munich, Germany Download Document: [Link]
Find more application cases here or contact us to get more information on real-life customer projects.