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IP & Library Design Challenges
A main application area of MunEDA´s WiCkeD design analysis, modeling and optimization tools and solutions is the specification-driven transistor-level sizing and analysis of standard I/O cells, I/O macro cells, and analog libraries. Many of these circuits have to keep tight specs on high-speed transient signals, under varying operating conditions, process conditions and mismatch. Sizing them manually by iterative parameter sweeps is time-consuming and does not produce optimum solutions. When libraries are developed for modern technologies, model file updates occur frequently and require updating the sizing of the cells each time.
MunEDA Tools for IP & Library Design
MunEDA WiCkeD contains a large toolbox of analysis, modeling and sizing tools. MunEDA WiCkeD contains high performance optimization methods that are specialized for performance tuning, robustness optimization, initial sizing and incremental sizing updates of IP libraries. Since batch mode operation is supported, WiCkeD has been successfully integrated into some customer-specific environments for automatic library updates.
Typical Application Areas for MunEDA WiCkeD in IP Libraries Design:
- Standard I/O cells, I/O macro cells, and analog libraries
- Sizing - Automate Sizing for IP Reuse and process technology (pdk) updates
- Optimization of precision transient signals
- Sizing for speed, robustness, area, leakage
- Statistical Variation & Corner Analysis
- Performance Optimization & Modeling
- Robustness & Yield Optimization
- Reduction of Area, Power & Consumption
- Initial Design (low voltage)
Typical Circuits for
IP & Library Design |
Typical Performance Metrics for
IP & Library Design |
- Transmitter
- PCIe Equalizer
- Receiver
- LVDS Drivers
- Clock Buffers
- Serializer/Deserializer (SerDes)
- Level Shifter
- Bandgap References
- Voltage Regulators
- Short/Overload Detectors
- Impedance Control Circuits
- Voltage Level Detectors
- Power-on-reset
- ...and more
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- Jitter
- Eye Diagram Opening
- Duty Cycle
- Temperature Stability
- Voltage Levels
- Delays
- PSRR
- Accuracy
- ...or similar
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Customer Success IP & library Design
with MunEDA WiCkeD Tools
David Wu, R&D Technical Director, Faraday Technology Corp.:
"We successfully used the script language provided by WiCkeD in the optimization plan to drive the porting process in less than 1,5 hours from 0,18µm to 90nm (including layout). Its quite impressive. The same task requires days of efforts for a regular designer. The simple setup procedure and intuitive flow make it a useful tool kit for automatic circuit optimization."
IP & Library Design
 Faraday - IP porting & Analog Synthesis Automation Platform using WiCkeDTM
 ZMDI - Analog IP Porting with WiCkeD
 Infineon - Optimization of I/O Macro Cells with WiCkeD
 IMMS - Reuse of Circuit Topologies using WiCkeD
Andreas Brüning, Director Technology Officer, ZMD AG, Dresden:
"After testing MunEDA´s design and yield optimization tool WiCkeD in some very successful pilot projects, we chose it for analysis and optimization of analog and mixed-signal circuits and towards increased yield and robustness of our golden IP library."
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