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Analog Circuit Verification Flow with MunEDA WiCkeD
Application Flows
Analog Circuit Verification Flow
Introduction by Marat Yakupov
(13:33 min)
Download Analog Circuit Verification Flow as PDF here: 
Benefits of Analog Circuit Verification with WiCkeD
- Increased Design Confidence prior to Tape-out
- Structured Reports for Design Reviews and Management
- Powerful Analog Circuit Verification Tools and Functionalities
- Fully integrated in Standard Design Environments
- Minimum effort required, Easy step-by-step guidance
- Support for ISO 26262 analysis requirements for automotive
Download (PDF):
Analog Circuit Verification Flow with MunEDA WiCkeD
Analog Circuit Verification - Motivation
To verify the best functionality and design quality is an essential part of today’s analog and mixed-signal circuit design. Circuit designers want to have powerful tools that deliver deep information and insides into circuit behaviour. At the same time these tools should be easy to set up and handle and deliver the required information quickly and comfortably.
Analog Circuit Verification – 3 Steps Flow with WiCkeD
The MunEDA WiCkeD Verification Suite delivers the designer an easy and simple 3-STEPS application flow to verify the circuit designs for the given requirements. Based on the designer’s circuit schematics, testbenches and netlists there are only a few simple and easy to do preparation steps in the design framework and in the WiCkeD tool suite itself.
WiCkeD Circuit Verification Tools Overview
WiCkeD contains different tools to verify circuit status and quality. Designers can easily check their designs for performance and process sensitivities, worst-case operating corners and partial and total design yield.
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Step 1 – Select & Prepare Circuit in Design Framework
Step 1 - Select & Prepare Circuit in Design Framework
- Select Circuit Schematic
- Prepare Single or Multi-Testbench
- Define Circuit Performances
- Define Extraction Statements
- Run Test Simulation
Select in your design framework the circuit toplevel schematic (DUT – Design under test) and prepare the required single or multiple testbenches. Define for the circuit the required performances and extraction statements and expressions with your used extraction language. To check run a simple test simulation to verify the circuit can be simulated. After this preparation simply start WiCkeD from tools section of your design framework.
Step 2 – Circuit Setup for Verification with WiCkeD
Circuit Setup for Verification with WiCkeD
- Read Circuit Netlist
- Assign Operation Parameters
- Physically Identical Instances
- Select Mismatch Parameters
- Define Performances Specifications
With the WiCkeD Constraint Editor you can automatically read-in the netlist of your selected DUT. Supported by some GUI-steps you assign the operating parameters and define the required operating ranges. In case of multi-testbenches you define also the physically identical instances. Finally you select the mismatch parameters and define the performance specifications for your circuit design.
Step 3 – Use WiCkeD Verification Tools and Generate Verification Reports Automatically
You now can start within WiCkeD history window fully GUI-supported all analysis and verification tools required for your specific verification demand. Based on circuit simulation with your standard SPICE or FastSPICE you verify your circuit for sensitivities, worst-case operating corners, global statistical variation and yield, high-sigma values and robustness, and many influence factors more.
Step 3 – Use WiCkeD Verification Tools and Generate Verification Reports Automatically
- Verify Circuit Sensitivities
- Verify Worst Casee Operations Corners
- Verify Global Statistical Variation & Yield
- Verify for High-Sigma and Robustness
- Generate Verification Reports Automatically
Circuit Verification with MunEDA Tools – Solutions that help!
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WiCkeD Tool Suite for automated design analysis, porting, verification, modeling and optimization of IC & IP design. |
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For more information and support contact www.muneda.com
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WiCkeD Interfaces & Platform Support:
- SUN-Solaris®, Linux, CentOS
- Full Graphical User Interface
- Documented API (C++, Tcl/Tk, Phyton, etc.)
- Parallel Simulator Interface (LSF, SGE, rsh, ssh)
- Export/Import Interfaces (Matlab, R, SPlus, Verilog-A, VHDL-AMS)
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WiCkeD Design Framework & Simulator Support:
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